CHAPTER 3
XAUI SYSTEM ARCHITECTURE
In this chapter, the 10 Gigabit Ethernet XAUI system is reviewed. This chapter also
includes the different features of Xilinx’s embedded PowerPC processor and 3.125 Gbps
RocketIO serial transceivers that were used for the development of the test system
The XAUI system consists of an XGXS (XGMII Extender Sublayer) at the RS end (DTE
XGXS) and an XGXS at the PHY end (PHY XGXS) separated by a XGMII extender
known as XAUI, the purpose of which is to extend the operational distance of the XGMII
and also reduce the number of interface signals. The DTE XGXS acts as an 8B/10B
encoder in one direction and as a decoder in the other direction, and the same is true of
the PHY XGXS. The 8B/10B encoding/decoding functionality is specified in clause 48 of
the IEEE 802.3ae standard-10GBASE-X PCS. The XGXS blocks are separated by XAUI
data paths spanning up to approximately 50 cm. The XAUI interface is optional if
implemented, should be implemented as a chip-to-chip interface with traces on a Printed
Circuit Board (PCB) and possibly a pluggable module or backplane connector.
The XAUI system’s architecture is shown in Figure 3.1.
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LAN
c s m
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LAYERS
HIGHER LAYERS
OSI
REFERENCE
MODEL
LAYERS
LLC—LOGICAL LINK CONTROL
MAG CONTROL (OPTIONAL)
APPLICATION
PRESENTATION
XGMII
XGXS
TRANSPORT
XGMII— M
NETWORK
PCS
DATA LINK
PHY
PHYSICAL
MDI
MEDIUM
MAC = MEDIA ACCESS CONTROL
PMA = PHYSICAL MEDIUM ATTACHMENT
MDI = MEDIUM DEPENDENT INTERFACE
PMD = PHYSICAL MEDIUM DEPENDENT
PCS = PHYSICAL CODING SUBLAYER
XAUI =1BGIGABITATTACHMENTUNIT INTERFACE
PHY = PHYSICAL LAYER DEVICE
XGMII = 10 GIGABIT MEDIA INDEPENDENT INTERFACE
XGXS = XGMII EXTENDER SUBLAYER
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