| Figure 5.7: lOGec Test system
After the capture has been stopped, the trig_addr signal indicates the final location where
the capture RAM was written. The PowerPC then waits for the user to download the
captured data via the serial interface using the Xmodem protocol. The PPC interfaces to
the capture RAM via the Logie_Analyzer OBP peripheral. Data is requested via the
peripheral from address 0x0000, to the trig_addr. Once 128 bytes of data have been
acquired by the peripheral, the PowerPC transmits 1 packet, waits for a positive ACK,
then proceeds to transmit the next 128 bytes of data. Once all packets have been
transmitted, the PowerPC pulses the trig ack signal, which resets the LAFSM back to the
idle state. The logic analyzer peripheral was designed using EDK8.2i. The peripheral is
made of 4 slave registers, each 32 bits wide, used for capturing data and other control
47
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
signals. The design has been verified functionally. However, the design could not be
verified on the evaluation board due to time constraints.
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