| 4.1 PCS Transmit Implementation
The system is designed around the Xilinx ML321 Virtex2 Pro evaluation platform. The
system is designed to interface with a PC running customized Lab View software to
upload /download data patterns, as well as control the board. I/O between the ML321 and
the PC is performed via the serial port of the ML321 board. This serial port is also used
to interface with the embedded Power PC processor.
Figure 4.1 illustrates the test setup employed throughout the testing process. The XAUI
interface of the Device Under Test (DUT) was used to provide access to the DUT in all
test cases. Control access to the DUT was provided via a serial port interface. The test
system consists of the PC, Lecroy SDA 6000 (DSO), Xilinx ML321 and the Spirent
Smartbits interfaces. The test setup described in this chapter is greatly simplified in the
next chapter. The Lecroy SDA 6000 (DSO) is replaced by a Logic Analyzer built into the
FPGA improve the overall reliability of the XAUI test system. The Spirent Smartbits was
also removed from the system.
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