The channel bonding feature was implemented on the Receive system to enable
calculation of inter-frame gap and also to enable the implementation of logic analyzer on
the board.
The Xilinx provided channel-bonding feature can be implemented only if the
CLK_CORRECT_USE attribute is set to true. This attribute enables the elastic buffer to
repeat or skip the clock correction sequences (Idle) to compensate for differences
between the clock recovered from serial data and the reference clocks. As a result the
apparent IFG from the DUT might be effectively increased or decreased for the clock
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correction process. Hence, it would be impossible to determine the exact true IFG
between the frames. If the channel bonding feature provided by Xilinx is set to FALSE,
the clock correction can be disabled. The RXRECCLK can be used to drive the Receive
logic in the fabric. Thus, there will be no problem of data overflow. However the channel
bonding has to be implemented by design changes.
The channel bonding feature was implemented using 4 different FIFOs. The data is
transmitted and received as 2 byte data. Each channel receives 2 bytes of data. The use of
multiple transceivers in parallel for higher data rates results in splitting words of data.
Each byte is sent over a separate channel or transceiver. The first byte of data is followed
by the fifth byte of data and the second byte of data is followed by sixth byte of data and
so on. Fig.5;2.2 shows the data sequence on each channel.
1st byte
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