Ep optima synopsis

European Commission

ESPRIT

Information Technologies RTD Programme

Domain 2:
Technologies for Components
and Subsystems

Summaries of projects

Fourth Framework Programme

March 1998

Directorate-General III

Industry

Legal notice

Neither the European Commission nor any person acting on behalf of the Commission is responsible for the use which might be made of the information in this document

This document was edited by

Colette Maloney

Esprit contact point

Esprit Information Desk

N-105 8/94
Avenue de Nerviens / Nerviërslaan 105
B-1040 Brussels

tel +32 / 2-296-8596 — fax +32 / 2-296-8388

e-mail [e-mail]
Web http://www.cordis.lu/esprit/home.html

Check for updates to this document on the Web

http://www.cordis.lu/esprit/src/projects.htm
Contents
Introduction iii

Acronym index v

Synopses

Application Competences and Design 1-1

Enhancement of Technology and Manufacturing Base 2-1
Microsystems 3-1
Peripherals 4-1
ESD Best Practice and Cooperative R&D 5-1
Design Clusters 6-1
Equipment Assessment (SEA) 7-1
Basic Services and First Users Action 8-1
Networks and Working Groups 9-1

Introduction

The present volume contains synopses of projects launched since 1995 under the ESPRIT programme (Fourth Framework Programme) in Technologies for Components and Subsystems.

The synopses provide brief summaries of the projects, their objectives and a list of the partners involved. Technical contact points, start dates and duration are also provided. The layout of this volume follows the thematic headings outlined below.
R&D projects for components and subsystems are structured around the following technical themes:

• 
  Semiconductor components and subsystems - Application competences and design
  

The objective is to provide electronic system manufacturers with innovative microelectronics components and subsystems for their future products. Adaptation of existing technologies through close cooperation of users and suppliers to provide new features or increased functionality (portability, endurance, performance, etc.) is the primary approach to broadening microelectronics applications.

• 
  Semiconductor components and subsystems - Enhancement of technology and manufacturing base
  

By the beginning of the next century, ICs will employ upwards of 50 million transistors, 5 to 6 layers of metal wiring and clock rates of over 1 GHz. Coupled with the move towards 300 mm wafers and critical dimensions of 0.18 microns, this poses challenges to all aspects of IC technology and manufacturing. At a process level, development of equipment and advanced process modules are among the activities addressed. At a system/subsystem level, packaging issues such as fine line multilayer PCBs, semiconductor area array packages and MCMs are covered, the focus being on cost and manufacturability rather than on performance.

• 
  Microsystems
  

A microsystem is defined as an intelligent, miniaturised system comprising sensing, processing and/or actuating functions, normally combining two or more of electrical, mechanical or other properties on a single chip or a multichip hybrid. Activities in microsystems aim to stimulate the establishment of an industrial microsystems supply, to expand the application potential of microsystems components and to foster the uptake of microengineering technologies in larger systems. Application areas include the automotive, medical, environmental, industrial and consumer sectors.

• 
  Peripherals
  

Peripherals technologies cover components and subsystems for displays and mass-storage systems. In display technologies, the approach is to focus on flat slim displays; mass storage concentrates on magneto-optical systems.
The following preparatory, support and transfer activities are undertaken:

• 
  ESD Best practice, cooperative R&D
  

Ongoing best practice activities in electronic systems design (ESD) aim at promoting use of state-of-the-art commercial design and validation of prototype tools to ensure the availability of future generations of design tools.

Cooperative research in ESD aims at the provision of tools, methodologies and services (with emphasis on system level and mixed signal design) to industrial user companies.

• 
  Design Clusters
  

The emergence of high volume applications, in particular communications systems, that can support the development of dedicated ICs poses challenges for designers in terms of achieving increased power savings and increased integration. Added to this, efficient design methodologies are required to ensure product development within increasingly shorter time-to-market constraints. The Design Clusters activity addresses both low power design and mixed-signal design, and focuses on methodology. Design experiments (which constitute either the low power cluster or the mixed-signal cluster) aim at developing or improving design and test methodologies for application in products.

• 
  Equipment assessment
  

The semiconductor industry is facing an ever-growing demand for components with decreasing critical device dimensions and an increasing wafer size. Up to 80% of the costs of a leading-edge wafer fab are due to manufacturing equipment alone. The Semiconductor Equipment Assessment (SEA) initiative is supporting European equipment suppliers by facilitating close links between them and global IC manufacturers. The activities include assessment of front-end, back-end, metrology, and FPD equipment.

• 
  SEA 300
  

A new action, called SEA300, has been launched to support 300 mm equipment Demonstration Tests at European suppliers' sites by providing 300 mm wafers (blank and preprocessed) and metrology services.

• 
  Basic Services and First Users action
  

Basic Services (EUROPRACTICE) offers a cost-effective and flexible means of accessing ASICs, MCMs and microsystems technologies through the provision of consultancy, training, software tools, design support and low-volume production runs. The costs of developing ASICs for dedicated applications with low-volume production are often prohibitively high, especially for SMEs. Multi Project Wafer (MPW) runs offer a cost-effective route to ASIC design and fabrication.

The First Users action (FUSE) aims to stimulate the take up of microelectronics technologies by enterprises in all sectors of industry. The application areas are many and diverse, often with niche markets. Through participation in FUSE, enterprises, in particular SMEs, learn that the implementation of microelectronics technologies provides an economically viable route to increased competitiveness. Through dissemination of actual case studies drawn from participants in FUSE, this message should be relayed to enterprises in all sectors of industry throughout Europe.

• 
  Networks and working groups
  

Networks and working groups have been set up to promote the use of advanced design technologies both in large enterprises and SMEs. In packaging and microsystems technologies, networks provide an infrastructure to facilitate the industrial cooperation needed to firmly establish design and manufacturing in these areas.

Acronym Index

Acronym Number Title Page

ABACUS	26530	Active Bus Adaptor and Controller for remote UnitS	6-19
ABEL	23218	Automated Back-End European Line	2-10
ACE	24115	Advanced CMOS for Europe	2-5
ACID-WG	21949	Working Group on Asynchronous Circuit Design	8-0
ACS	25296	Microsensor system for automatic process control in a food industry	3-11
ADEQUAT+	21752	Advanced Developments for CMOS for 0.25 micron and Below	2-3
ADTV	22249	ASIC Design Transfer using VHDL	5-10
ALBATROS	22826	A Logistic Bi-directional Asyncrhonous Tag-system for Retail OperationS	1-4
ALPINS	25485	Analogue Low Power Design for Communications Systems	6-11
AMADEUS	21812	Analogue Modelling and Design using a Symbolic Environment	1-25
AMIED	25249	Asynchronous Low-Power Methodology and Implementation of an Encryption/Decryption System	6-4
AMITY	21261	Analogue mixed-signal sub-micron Design Test System	1-22
APC	24030	Advanced Photomask Cleaning	7-12
APPLE	21981	Advanced Polishing and Planarization Equipment	7-14
ASIC4PMR	23989	Architecture for Single Chip for Private Mobile Radio	1-7
AUDICO	21570	Multi-chip module Automotive Digital Core for Electronics Control Unit	1-13
AUTOWET	20757	Automated Wet Bench for critical pre-oxidation Treatments for sub-half micron Applications	7-13
AWARE	22966	Anti-Collision Warning and Avoidance Radar Equipment	3-7
BAGINEA	24364	Ball grid array inspection equipment assessment	7-25
BATEL	24366	Ball Grid Array Technologies for Advanced Telecom Applications	2-15
BETA	23229	Bipolar Epitaxial Si/SiGe Technologies for RF Applications	2-20
BLUE BIRD	21657	High Capacity blue source based magneto-optical disc drive dedicated to network integration	4-3
CAME	20445	Cleaning Assessment in a Mini-fab Environment	7-4
CATG	23104	Coverage Analysis and Test Generation	5-34
CICDIP	20628	Hot Cluster for Integrated Vapour Phases Cleaning and Processing of Dielectrics and in-situ doped Polysilicon	7-5
COCLICO	23246	COntact/ContactLess Interoperable microCOntroller based Smart Card system	1-6

COLOPODS	25475	Design of a Cochlear Hearing Aid Low-Power DSP System	6-9
COOL-LOGOS	25279	Power Reduction through the Use of Local don’t Care Conditions and Global Gate Resizing Techniques : An Experimental Evaluation	6-6
CORE	23237	Core Processor Implementation for ADSL Telecom Applications	5-36
COTRED	22350	Cost of Test Reduction: Assessment of IC Tester for High Volume and Digitized Analogue Applications	7-24
CRAFT	25710	CMOS Radio Frequency Circuit Design for Wireless Application	6-17
CUMULUS	23769	Development of a generic, low cost MCM-L technology for use in portable consumer, automotive and industrial applications	2-12
DABLP	25518	Low Power Exploration for Mapping DAP Applications to Multi-Processors	6-12
DAMASCENE	25220	Damascene Architecture for Multilevel Interconnections	2-6
DEEMO	20342	Dry Etching, Electroplating and Moulding	3-1
DEMOMAG	22253	Design and Modelling improvement of Magnetic Components in Power Electronics for Aerospace Applications	5-11
DESCALE	25519	Design Experiment on a Smart Card Application for Low Energy	6-13
DRIVE	22103	Design for Electronic Drive Control	5-5
EARNEST	21972	ECSI Awareness Reflection Network for ESD Technology Standards	9-5
ECAM III	20310	European Consortium Active Matrix III	4-1
ECU	22408	Design and Product Development of New Generation of ECU	5-31
EDGE	21404	Enhanced Design of GaAs in Europe	1-23
EDUSA	20747	European Deep UV Stepper Assessment	7-7
EESD	20702	Enhancement of Electronic System Design by EMC Adviser System	5-27
ELDISP	22575	Next Generation Colour Electroluminescent Displays	4-4
ELDS	23166	L-STRIPPER - Assessment of an excimer laser based tool to achieve perfect dry single step resist and polymer stripping for sub-micron technology	7-11
ELECLINE	21314	Electrical Line for Competitive and full Compatible Household Goods, Communications and Utility Equipment	4-12
ELLIPSE	21760	Excimer Laser Lithography Project for sub-quarter micron Era	2-7
EMCLO	22409	EMC Design Methodologies for PCB Layout Optimisation	5-12

EMCPCB	20755	Using new Concepts to obtain EMC on PCBs	5-3
EMMEA	22206	Electromigration Monitoring Equipment Assessment	7-23
EMW	20305	Evaluation of a Highly Productive, Computer-Controlled Microwave Barrel Ash System for IC Fabrication	7-1
ENPROCO	22169	Enhanced Processor-based System for Electronic Control Applications	5-8
ESAMA	22205	European Scanning Acoustic Microscope Assessment	7-22
ESCAPE-NET	20580	Total Environment Fab Waste Gas Management via Networked and Monitored Escape Disposal Systems	7-15
ESCHETA	26245	European Sources of Chip Scales Packages for Harsh Environment, Telecom & Automotive	2-16
ESDEM	23643	ESD Protection Design Methodology	1-27
EUROPRACTICE	21101	Promoting Access to Microelectronics Technologies for Industrial Competitiveness in Europe	9-1
FANETA	26233	Failure Analysis plasma etch equipment assessment	7-26
FASTTRACC	20378	Formal Design Validation	5-19
FED	22659	Development of a 5.2 " FED Colour Display	4-6
FIPSOC	21625	Field Programmable System on Chip	1-24
FLASH PT 300	25991	Future Leadership through assessment of high quality production tool for 300 mm Wafers	7-28
FLINT	23261	Fine Line Interconnect	2-11
FLIPAC	26280	Fine Line Interconnection an Packaging	2-18
FORCE FILL	20390	Sigma 204 Force Fill Assessment for 0.5 micron contact/via (Al/0.5 %Cu) Plug Technology in a High Volume Production Environment	7-3
FORSITE	23037	FORMAT Software in an Industrial Environment	5-16
FUSE	21963	First Users Action	8-2
GAMMA	21315	Gallium Arsenide Material for Microwave Applications	2-19
GAP	21667	Gas based EHS Products for Existing Dwellings	4-14
GERTRUDE	22415	Printed Circuit Board CAD/CAM data Transfer using EDIF	5-13
GOOD-DIE	20797	Get Organised Our Dissemination of Die Information in Europe	2-9
GOOD-DIE NETWORK	20796	Get Organised Our Dissemination of Die Information in Europe	9-2
HARCODA	20413	Hardware Realisation of Communication Coding Algorithms	5-22
HEARMASTER	20482	Advanced Hearing Aid Test Tools in OTICON	5-1
HIPERPRINT	24363	High Performance Printed Boards and Subassemblies for Telecom and RF Applications	2-14
HIPOCRAT	23199	Human implantable prosthesis offering cardiac rhythm assistance therapy	1-16

HRAS	20649	High Resolution Analytical REM	7-19
ILETIC	22072	In-line Ellipsometer for Thickness Control	7-20
IMALP	21245	Implantable Microsystems for Augmented Liver Perfusion	3-13
I-MODE	25702	Low Power RF to Baseband Interface for Multi-Mode Portable Phones	6-16
IMPASS	23910	Integration of Magnetics and Passive Components	2-13
IMPROVE	20379	In-line Monitor for Process Optimisation and Verification	7-18
IN-RAM	26320	Intelligent RAM Component for Streaming Applications	1-14
INTACT	25190	Intelligent Automotive Actuator Control & Communication Techniques	3-8
IRMA	21796	Integrated Resonant accelerometer Microsystems for Automotive applications	3-5
LAMPADY	25498	Large Multimedia Plasma Display	4-10
LAP	26261	Low cost Large Area Panel Processing of MCM-D Substrates and packages	2-17
LAPS	23929	Large Area Synthetic Fused Silica Photomask Substrates for 0.18 µm CMOS Technology	7-10
LAYSYN	20508	Physical Design Synthesis	1-21
LIPP	20771	Very large flat Plasma Display Panel for Industrial Process Control	4-2
LOVO	25248	Low Output Voltage DC/DC Converters for low Power Applications	6-3
LP-DSP	21482	Low Power and cost DSP subsystems for portable products	1-1
LPGD	25256	A Low-Power Design Methodology/Flow and its Application to the Implementation of a DCS1800-GSM/DECT Modulator/Demodulator	6-5
MAGIC	20360	Magnetic Integrated Circuits for Industrial Switch and Sensor Applications	3-2
MCC	22818	Design of Motion Control Chip	5-32
MEDID	21807	Microelectronics for large area, high resolution, real-time, flat, Digital Image Detectors	1-15
METEOR	22158	Metrology Equipment Test for Overlay Reading for sub-half micron Technology	7-21
MIRS	20679	Micromachined Integrated Relay System	3-3
MISIDESY	20816	Closed front to back end mixed-signal ASIC Design System	5-4
MLS	20385	Design of an Interface ASIC for RISC Systems using a VHDL based "Independent" Environment	5-20
MOSAREL	25340	Monocrystalline Silicon Active Matrix Reflective Valve Light	4-7
NETPACK	21468	Network for Packaging	9-3
NEW EMPHASIS	23222	Enhanced Mobile Phone with Application Specific Memory System	1-5

NEXUS	20713	Network of Excellence in Multifunctional Microsystems	9-6
NICE	22982	Real-time 3d ultrasound imaging system with advanced transducer arrays	3-14
OCMP	24123	One-Chip Low Power Transceiver for Multi-Mode Portable Phones	1-9
OLMO	22889	On-vehicle Laser Microsystem for Obstacle Detection	3-6
OPTIMA	23928	Optical Proximity Techniques in Microelectronics Applications	7-8
OPTISSIMO	22821	Evaluation and Demonstration of the Optical Proximity Correction and Simulation Tool OPTISSIMO	5-14
OSIM CHIPSET	21227	Open and Scaleable Intelligent Metering System Chipset	1-18
OSIM-AHSII	21499	Open and Scaleable Intelligent Metering System for Advanced Home Services II	4-13
OSSWLAN	23181	Optimized Spread Spectrum Wireless - LAN	5-35
PAPRICA	25476	Power and Part Count Reduction innovate Communication Architecture	6-10
PARFUM	20848	Process control and Air cleaner applications with Recognition of gases and Flavours Using a smart Microsystem	3-9
PARIS	22105	Usability, Optimisation and Productivity Enhancement of the Integrated Layout Tool PARIS	5-6
PASCALE	25558	Parasitic Substrate Coupling Analysis by Layout Extraction	5-37
PCASIC	20605	Personal Computer tools for the Design of Application Specific Integrated Circuits	5-26
PCBIT	25716	Low Power ISDN Interface for Portable PC’s	6-18
PHOSPAP	22615	Development of Vacuum Ultraviolet (VUV) Phosphors for Large Plasma Display Panels	4-5
PLASMON	25470	Assessment of Advanced Plasma diagnostic tools for in-situ process Control and Monitoring	7-6
PLUTO	22106	Reduced Design Time using PLUTO Demonstrator Vehicle	5-29
PODSIM	20883	Simulator Pod supporting multiple S2m Links	5-28
PREST	25242	Power Reduction for System Technologies 6-1	6-2
PROSAFE	24097	Software-supported Prototyping and Real-time Implementation of Intelligent Multisensor-based Safety Control Systems	5-17
PROXIMA	23224	Programmable Maximum Integrated Electronic Trip	1-19
QESDI	20455	Quantification of ESD Economic Impact for SMEs	5-23
QUANTUM	21152	Sensors for Chemical Species based on Luminescence Decay Time Measurement	3-12
RETIMATIC	22207	Dual Carousel semi-automatic Reticle Stocker	7-17

ROBAS	24359	ROBust ASICs for automotive	1-17
SALOMON	25615	System-level analog-digital trade-off analysis for low power	6-15
SB-USB	25599	Software Based Universal Serial Bus	6-14
SCARF	24315	Smart Communicating Applications using Radio Frequency	1-20
SCHINET	23223	Single Chip ISDN Network Termination	1-11
SCOTSMAN	21674	Strategic Components, Technologies and Systems in Magnetic Storage	4-11
SEA	23657	SEA 300	7-27
SE-BN-LCD	25187	Surface Effect Bistable Nematic Liquid Crystal Displays	4-8
SECOND	21680	Single ended Channel Conditioning Device	1-2
SEED	22797	Supplier Evaluation and Exploitation of DELPHI	1-26
SEED	22133	Software/Hardware Exploration: a European Demonstration Project	5-7
SEM-A-HDL	20548	Smart Energy Meter Design using novel CAD tools that support Analogue HDL modelling techniques	5-25
SHAPE	20763	Sub-half micron CMOS Process for European Users	2-2
SI_GYRO	21458	Silicon Surface Micromachined Gyroscope for Mass Market Applications	3-4
SIDOSI	20331	Single Wafer highly n+ and p+ doped Amorphous and Polysilicon Deposition	7-2
SIFGEN	26698	Software Interface Function Generator	5-38
SMOG	21428	Smart Air Pollution Monitoring Network	3-10
SOFLOPO	25403	Low Power Software Development for Embedded Applications	6-8
SOGROUTE	20491	Physical Design Automation on mixed semi-custom Arrays	5-2
SPACE	24006	SOI for Portable Applications and Consumer Electronics	1-8
STARLIGHT	21587	The Starlight Core for Express Disk Drive Controllers	1-10
STAY ON	20509	ASIC Solution for Dedicated TV Camera	5-24
SUMMIT	20492	Silicon Substrate multi-chip modules for Innovative Products	2-8
SUPREGE	25400	A low power SUPerREGEnerative transceiver for wireless data transmission at short distances	6-7
SYNC	20388	High level Synthesis of a Remote I/O for a Numerical Control System	5-21
SYSLINK	20307	Euro-Syslink	9-4
TACTIC	24268	Test Applications concerted for Telecom Industry Challenges	5-18
TARDIS	25213	Design Clusters Technical Coordination and Dissemination	6-1
TIBIA-II	20485	Technology Initiative in BiCMOS Applications	2-1

TRAMST	25644	Transformers using MicroSystems Technology	3-15
TRIO	23042	Optimally integrated vacuum/abatement/monitoring equipment for demanding semiconductor manufacturing processes (TRIO-VAMP)	7-16
TWICS	21785	Technological Solutions for Wireless Communications Subsystems	1-3
TWIST	24137	Twin Carrier Single Transceiver Base Station for PCS	1-12
ULTRA	23806	Ulsi mosT Research Activity	2-4
VISUFLEX	25224	Bistable Reflective FLC Displays on Plastic Substrates for smart cards	4-9
VITALISE	22203	VXI Industrial Test Applications for Liaison with IEEE 1149.1 System Environments	5-9
VMUSB	23051	VHDL Model of Universal Serial Bus to ISA Bus Adapter	5-33
VSDSE	22342	VHDL-based System Design and Simulation Environment	5-30
YETI	22979	Yield simulation and enhancement Tool YETI	5-15

Application Competences and Design

EP 21482 LP-DSP

Low Power and Cost DSP Subsystems for Portable Products

Summary

The LP-DSP project aims at creating a capability to develop low power and low cost IC implementations of DSP applications. The capability will consist of an integrated design system, the necessary module/cell libraries and the target silicon process. The design system will be based on a state-of-the-art architectural synthesis tool that will be further developed in the project for power optimisation. The capability will be demonstrated by designing and implementing a subsystem for a mobile/cordless phone product.

Objectives

· An ASIC hard macro implementation of a DSP subsystem of a DECT mobile phone product featuring very low power consumption, dense layout (low cost) and adequate performance.

· A prototype chip containing the developed ASIC hard macro and associated measurement results.

· A high level architectural synthesis tool capable of power consumption optimisation and allowing the use of a wide variety of application specific execution units.

· A library of DSP modules that can be used as application specific execution units in the above mentioned synthesis tool.

· A library of standard cells for SGS-Thomson Microelectronics' 0.35 micron technology optimised for low power consumption.

· A library of macros and layout generators for SGS-Thomson Microelectronics' 0.35 micron technology optimised for low power consumption.

· Interfaces that are needed between the developed/existing tools/libraries to provide a seamless design path for ASICs.

Participants__SGS-Thomson_('>Participants__Informatica_el_Corte_Ingles_(E)'>Participants__GPS_(UK'>Participants__Alcatel_SESA_(E);'>Participants__Nokia_(SF'>Participants

Nokia (SF), SGS-Thomson Microelectronics (F), European Development Centre N.V. (B), Tampere Univ. of Technology (SF)
Contact Point Duration

Klaus Kronlof 30 months from 15.02.96

Nokia Research Center

P.O. Box 45 Fin-00211 Helsinki (Finland)
tel: [phone]

fax: [phone]

E-mail: [e-mail]

EP 21680 SECOND

Single Ended Channel Conditioning Device
Summary

The continuous growth of the subscriber base in current mobile systems, i.e. Digital European Cordless Telecommunication, (DECT), system provides a motive to seek new ways of increasing the capacity on offer. One approach is to improve signal quality by using advanced signal processing techniques. The added value of this approach with respect to already existing solutions, namely HDSL and ADSL, is that the signal processing will only be done at one line termination of the digital local line. This contrasts with HDSL that requires signal processing at both line terminations of the digital local line. The outcome of these activities will be a connector-like module attachable between Base Station (BS) and the wire towards the Base Station Controller (BSC). Improvement of the air interface of DECT with the same single-ended concept to make it robust against multipath propagation will also be addressed.

Objectives

· The main objective is to develop a self-contained, very low volume, remotely powered signal conditioning subsystem to improve, for current DECT picocell system, the link quality in both directions of the communication in the wire interface between BS and BSC. The ultimate goal is to integrate this conditioning mechanism in a connector-like module for BS to BSC links allowing wire links up to 3 km.

· To demonstrate in field trials the performance and feasibility of the device.
Secondary goals whose achievement is crucial for accomplishment of the main goals are:

· To develop an ASIC capable of performing, in one single location, channel conditioning for bidirectional end-to-end links.

· To develop a high density DC/DC conversion module, incorporating advanced packaging of magnetic devices, to be included in the connector-like solution to allow remote powering for both functions in the conditioning device and BS from BSC.
· To demonstrate the signal conditioning architecture by means of a suitable feasibility model for the radio link, to achieve BER=10^-3 at 200 ns of delay spread.
Participants

Alcatel SESA (E); UPM (E); IMEC (B); Alcatel Mietec (B); NMRC (IRL); Cetecom (E)
Contact Point Duration

Mariano Perez Abadia 24 months from 01.03.96

ALCATEL SESA

Ramirez de Prado 5

28045 Madrid (Spain)
tel: [phone]

fax: [phone]

E-mail: [e-mail]

EP 21785 TWICS

Technological Solutions for Wireless Communications Subsystems
Summary

Micro miniature radio hardware solutions are to be developed for mobile phone and Wireless Local Area Network (W-LAN) applications. Existing advanced IC, MCM, interconnection and subsystem integration technologies will be modified and optimised to provide reduced cost, smaller size and lower weight, portable communications product components. The integration of the TWICS technologies will be demonstrated in a set of wireless communications hardware functions.

Objectives

· The modification and unification of existing advanced IC, MCM, interconnection and subsystem integration technologies to realise lower cost, smaller size and lower weight wireless communications subsystems hardware.

· The generation of integrated design rules for the optimised IC, RF MCM-D, circuit card and assembly integration technologies.
· The design and manufacture of cellular radio function components, using MCM-D technology for RF integration, chip sized IC packaging and advanced circuit card technologies.
· The design and manufacture of a flip chip MCM technology demonstrator for a 5.2 GHz W-LAN application.
Participants

GPS (UK); Ericsson Mobile Communications (S); STP Elektronische Systeme (D); GMMT (UK); Bull (F)
Contact Point Duration

Professor David J. Pedder 24 months from 01.02.96

GEC Plessey Semiconductors

Cheney Manor

Swindon

Wilts SN2 2QW (United Kingdom)
tel: [phone]

fax: [phone]

E-mail: [e-mail]

EP 22826 ALBATROS

A Logistic Bi-directional Asyncrhonous Tag-system

for Retail OperationS

Summary

Retail Business is involves three different type of operations, all of them strongly based on product identification systems:

• 
  Logistic operations (control of the different states that items can pass through)
  
• 
  Sales operations (computer aided check-out, goods returns, money refund,...)
  
• 
  Security operations (basically Electronic Article Surveillance, EAS systems)
  

Nowadays, the most popular method for goods identification is the bar-code system. This method requires the alignment of individual goods in front of an optical reader. It is prone to errors due to label abrasion or misalignment with the reader and does not provide a solution for the three operational problems above mentioned. New technology is required to implement a cost-effective identification system for goods and products that can offer functionalities which satisfy three operation areas of the retail business; allowing:

• 
  Identification with high reliability for logistic operations
  
• 
  Automatic check-out for sales operations
  
• 
  EAS System for security operations
  

The technology developed in ALBATROS will enable retailers to put in place tag electronic identification systems which will greatly improve many aspects of the retail business.
Objectives

· The aim of ALBATROS is the development of a new identification system for goods and products that can be used in the areas where product identification is needed and using just one tag independently of the type of identification required.

· The objective of the unique tag to be developed under this project is to provide higher reliability in the logistic operations, enable automatic check out in our stores and make the EAS system more efficient. The tag will use RF/ID technology. The areas covered will be ASIC, Tag, R/W equipment and the Information System. The project results will be shown in a pilot installation which will be set up in a selected department of ECI’s Department Stores.
 The results will be applied in different steps, starting from products of higher value in the garment area to reach the ultimate goal of the project that is to identify all products in the supermarket.
Participants

Informatica el Corte Ingles (E), Mikron (a), El Corte Ingles (E), Philips (D)
Contact Point Duration

Rodrigo Becerra 24 months from 01.11.1996

Informatica El Corte Inglés, S.A.

Travesia Costa Brava, 4

28034 MADRID (Spain)
tel: [phone]

fax: [phone]

E-mail: [e-mail]

EP 23222 NEW EMPHASIS

Enhanced Mobile Phone with Application Specific Memory System
Summary

The aim of the project is the development of an application specific memory integrating flash and EEPROM functions on the same chip for use, amongst others, in cellular phone applications. This innovative semiconductor device will be developed by the semiconductor company, SGS-Thomson, to the specifications determined by cellular phone manufacturer Nokia who will include the device in a phone demonstrator. Characterisation and process reliability studies will be undertaken at the IMEL research institute.

A new non-volatile memory cell concept will be developed in order to integrate both flash and EEPROM memory structures on the same chip without any increase in manufacturing complexity.

Objectives

• 
  The main objective of the project is to deliver a full featured 1.8GHz GSM phone incorporating a prototype of the integrated embedded applications specific memory system developed in the project. The prototype phone will be tested with the Nokia standard validation procedure which includes, amongst others, durability testing at high and low temperatures;
  
• 
  The application specific memory will be initially manufactured in 0.6 µm technology and be shrinkable to 0.5 µm.
  
• 
  The successful completion of the project will provide the opportunity for SGS-Thomson customers to have developed application specific memories combining customisable quantities of flash and EEPROM function for use in a very broad range of market sectors.
  

Participants

SGS-Thomson (I), Nokia NMP (SF), SGS-Thomson (F), Imel (GR)
Contact Point Duration

Dr. Giulio Iannuzzi 18 months from 01.10.96

SGS-Thomson Microelectronics

via Olivetti, 2

20041 Agrate Brianza, (Italy)
Tel: [phone]

Fax: [phone]

E-mail: [e-mail]

EP 23246 COCLICO

COntact/ContactLess Interoperable microCOntroller

based Smart Card system
Summary

The COCLICO project aims at the development of an interoperable bi-compatible contact/contactless Smart Card system based on a secure single chip microcontroller. The main target application is a combined Transport Ticketing and Electronic Payment card. The COCLICO project will develop a Smart Card System that combines ISO7816 contact with “remote coupling” (10 cm distance) contactless operation.

The COCLICO microcontroller IC and its tailored microcode will provide the high security level required for banking applications, with the necessary programmable flexibility to adapt the security algorithms to national regulations or specific application needs. It will also feature the contactless operation required for public transport ticketing applications with a fast transaction time.

The COCLICO terminal interface IC and its associated control software will assure Card-to-Terminal and Terminal-to-Card compatibility established in this system specification for contactless operation.

Objectives

· Specification and performance that meet world-wide market needs and standards

· R&D and design of a contactless/contact secure microcontroller chip
· R&D and design of a companion terminal Interface chip
· Development of a cost effective Smart Card assembly process
· Break-through in low-cost Terminal architecture
 Stable and secure microcode for the contactless functions of the Smart Card and Terminal Subsystem
 Scientific contributions to the emerging ISO 14443 standard for contactless type 2 systems
Participants

Gemplus (F), Motorola (CH, UK, F), Amex (UK), Sistema 4b (E)
Contact Point Duration

Olivier Trebucq 24 months from 01.09. 96

GEMPLUS

rue Guynemer, 34

92447 ISSY LES MOULINEAUX CEDEX (France)
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EP 23989 ASIC4PMR

Architecture for Single Chip for Private Mobile Radio
Summary