Technologies for Components
Summaries of projects
Fourth Framework Programme
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http://www.cordis.lu/esprit/src/projects.htm Contents Introduction iii
Acronym index v
Application Competences and Design 1-1
Enhancement of Technology and Manufacturing Base 2-1
ESD Best Practice and Cooperative R&D 5-1
Design Clusters 6-1
Equipment Assessment (SEA) 7-1
Basic Services and First Users Action 8-1
Networks and Working Groups 9-1
The present volume contains synopses of projects launched since 1995 under the ESPRIT programme (Fourth Framework Programme) in Technologies for Components and Subsystems.
The synopses provide brief summaries of the projects, their objectives and a list of the partners involved. Technical contact points, start dates and duration are also provided. The layout of this volume follows the thematic headings outlined below.
R&D projects for components and subsystems are structured around the following technical themes:
Semiconductor components and subsystems - Application competences and design
The objective is to provide electronic system manufacturers with innovative microelectronics components and subsystems for their future products. Adaptation of existing technologies through close cooperation of users and suppliers to provide new features or increased functionality (portability, endurance, performance, etc.) is the primary approach to broadening microelectronics applications.
Semiconductor components and subsystems - Enhancement of technology and manufacturing base
By the beginning of the next century, ICs will employ upwards of 50 million transistors, 5 to 6 layers of metal wiring and clock rates of over 1 GHz. Coupled with the move towards 300 mm wafers and critical dimensions of 0.18 microns, this poses challenges to all aspects of IC technology and manufacturing. At a process level, development of equipment and advanced process modules are among the activities addressed. At a system/subsystem level, packaging issues such as fine line multilayer PCBs, semiconductor area array packages and MCMs are covered, the focus being on cost and manufacturability rather than on performance.
A microsystem is defined as an intelligent, miniaturised system comprising sensing, processing and/or actuating functions, normally combining two or more of electrical, mechanical or other properties on a single chip or a multichip hybrid. Activities in microsystems aim to stimulate the establishment of an industrial microsystems supply, to expand the application potential of microsystems components and to foster the uptake of microengineering technologies in larger systems. Application areas include the automotive, medical, environmental, industrial and consumer sectors.
Peripherals technologies cover components and subsystems for displays and mass-storage systems. In display technologies, the approach is to focus on flat slim displays; mass storage concentrates on magneto-optical systems.
The following preparatory, support and transfer activities are undertaken:
ESD Best practice, cooperative R&D
Ongoing best practice activities in electronic systems design (ESD) aim at promoting use of state-of-the-art commercialdesign and validation of prototype tools to ensure the availability of future generations of design tools.
Cooperative research in ESD aims at the provision of tools, methodologies and services (with emphasis on system level and mixed signal design) to industrial user companies.
The emergence of high volume applications, in particular communications systems, that can support the development of dedicated ICs poses challenges for designers in terms of achieving increased power savings and increased integration. Added to this, efficient design methodologies are required to ensure product development within increasingly shorter time-to-market constraints. The Design Clusters activity addresses both low power design and mixed-signal design, and focuses on methodology. Design experiments (which constitute either the low power cluster or the mixed-signal cluster) aim at developing or improving design and test methodologies for application in products.
The semiconductor industry is facing an ever-growing demand for components with decreasing critical device dimensions and an increasing wafer size. Up to 80% of the costs of a leading-edge wafer fab are due to manufacturing equipment alone. The Semiconductor Equipment Assessment (SEA) initiative is supporting European equipment suppliers by facilitating close links between them and global IC manufacturers. The activities include assessment of front-end, back-end, metrology, and FPD equipment.
A new action, called SEA300, has been launched to support 300 mm equipment Demonstration Tests at European suppliers' sites by providing 300 mm wafers (blank and preprocessed) and metrology services.
Basic Services and First Users action
Basic Services (EUROPRACTICE) offers a cost-effective and flexible means of accessing ASICs, MCMs and microsystems technologies through the provision of consultancy, training, software tools, design support and low-volume production runs. The costs of developing ASICs for dedicated applications with low-volume production are often prohibitively high, especially for SMEs. Multi Project Wafer (MPW) runs offer a cost-effective route to ASIC design and fabrication.
The First Users action (FUSE) aims to stimulate the take up of microelectronics technologies by enterprises in all sectors of industry. The application areas are many and diverse, often with niche markets. Through participation in FUSE, enterprises, in particular SMEs, learn that the implementation of microelectronics technologies provides an economically viable route to increased competitiveness. Through dissemination of actual case studies drawn from participants in FUSE, this message should be relayed to enterprises in all sectors of industry throughout Europe.
Networks and working groups
Networks and working groups have been set up to promote the use of advanced design technologies both in large enterprises and SMEs. In packaging and microsystems technologies, networks provide an infrastructure to facilitate the industrial cooperation needed to firmly establish design and manufacturing in these areas.
Acronym Number Title Page
Active Bus Adaptor and Controller for remote UnitS
Bistable Reflective FLC Displays on Plastic Substrates for smart cards
VXI Industrial Test Applications for Liaison with IEEE 1149.1 System Environments
VHDL Model of Universal Serial Bus to ISA Bus Adapter
VHDL-based System Design and Simulation Environment
Yield simulation and enhancement Tool YETI
Application Competences and Design
EP 21482 LP-DSP
Low Power and Cost DSP Subsystems for Portable Products
The LP-DSP project aims at creating a capability to develop low power and low cost IC implementations of DSP applications. The capability will consist of an integrated design system, the necessary module/cell libraries and the target silicon process. The design system will be based on a state-of-the-art architectural synthesis tool that will be further developed in the project for power optimisation. The capability will be demonstrated by designing and implementing a subsystem for a mobile/cordless phone product.
· An ASIC hard macro implementation of a DSP subsystem of a DECT mobile phone product featuring very low power consumption, dense layout (low cost) and adequate performance.
· A prototype chip containing the developed ASIC hard macro and associated measurement results.
· A high level architectural synthesis tool capable of power consumption optimisation and allowing the use of a wide variety of application specific execution units.
· A library of DSP modules that can be used as application specific execution units in the above mentioned synthesis tool.
· A library of standard cells for SGS-Thomson Microelectronics' 0.35 micron technology optimised for low power consumption.
· A library of macros and layout generators for SGS-Thomson Microelectronics' 0.35 micron technology optimised for low power consumption.
· Interfaces that are needed between the developed/existing tools/libraries to provide a seamless design path for ASICs.
Nokia (SF), SGS-Thomson Microelectronics (F), European Development Centre N.V. (B), Tampere Univ. of Technology (SF)
Contact Point Duration
The continuous growth of the subscriber base in current mobile systems, i.e. Digital European Cordless Telecommunication, (DECT), system provides a motive to seek new ways of increasing the capacity on offer. One approach is to improve signal quality by using advanced signal processing techniques. The added value of this approach with respect to already existing solutions, namely HDSL and ADSL, is that the signal processing will only be done at one line termination of the digital local line. This contrasts with HDSL that requires signal processing at both line terminations of the digital local line. The outcome of these activities will be a connector-like module attachable between Base Station (BS) and the wire towards the Base Station Controller (BSC). Improvement of the air interface of DECT with the same single-ended concept to make it robust against multipath propagation will also be addressed.
· The main objective is to develop a self-contained, very low volume, remotely powered signal conditioning subsystem to improve, for current DECT picocell system, the link quality in both directions of the communication in the wire interface between BS and BSC. The ultimate goal is to integrate this conditioning mechanism in a connector-like module for BS to BSC links allowing wire links up to 3 km.
· To demonstrate in field trials the performance and feasibility of the device.
Secondary goals whose achievement is crucial for accomplishment of the main goals are:
· To develop an ASIC capable of performing, in one single location, channel conditioning for bidirectional end-to-end links.
· To develop a high density DC/DC conversion module, incorporating advanced packaging of magnetic devices, to be included in the connector-like solution to allow remote powering for both functions in the conditioning device and BS from BSC.
· To demonstrate the signal conditioning architecture by means of a suitable feasibility model for the radio link, to achieve BER=10-3 at 200 ns of delay spread.
Technological Solutions for Wireless Communications Subsystems Summary
Micro miniature radio hardware solutions are to be developed for mobile phone and Wireless Local Area Network (W-LAN) applications. Existing advanced IC, MCM, interconnection and subsystem integration technologies will be modified and optimised to provide reduced cost, smaller size and lower weight, portable communications product components. The integration of the TWICS technologies will be demonstrated in a set of wireless communications hardware functions.
· The modification and unification of existing advanced IC, MCM, interconnection and subsystem integration technologies to realise lower cost, smaller size and lower weight wireless communications subsystems hardware.
· The generation of integrated design rules for the optimised IC, RF MCM-D, circuit card and assembly integration technologies.
· The design and manufacture of cellular radio function components, using MCM-D technology for RF integration, chip sized IC packaging and advanced circuit card technologies.
· The design and manufacture of a flip chip MCM technology demonstrator for a 5.2 GHz W-LAN application.
GPS (UK); Ericsson Mobile Communications (S); STP Elektronische Systeme (D); GMMT (UK); Bull (F) Contact Point Duration
Security operations (basically Electronic Article Surveillance, EAS systems)
Nowadays, the most popular method for goods identification is the bar-code system. This method requires the alignment of individual goods in front of an optical reader. It is prone to errors due to label abrasion or misalignment with the reader and does not provide a solution for the three operational problems above mentioned. New technology is required to implement a cost-effective identification system for goods and products that can offer functionalities which satisfy three operation areas of the retail business; allowing:
Identification with high reliability for logistic operations
Automatic check-out for sales operations
EAS System for security operations
The technology developed in ALBATROS will enable retailers to put in place tag electronic identification systems which will greatly improve many aspects of the retail business.
· The aim of ALBATROS is the development of a new identification system for goods and products that can be used in the areas where product identification is needed and using just one tag independently of the type of identification required.
· The objective of the unique tag to be developed under this project is to provide higher reliability in the logistic operations, enable automatic check out in our stores and make the EAS system more efficient. The tag will use RF/ID technology. The areas covered will be ASIC, Tag, R/W equipment and the Information System. The project results will be shown in a pilot installation which will be set up in a selected department of ECI’s Department Stores.
The results will be applied in different steps, starting from products of higher value in the garment area to reach the ultimate goal of the project that is to identify all products in the supermarket.
Informatica el Corte Ingles (E), Mikron (a), El Corte Ingles (E), Philips (D)
Contact Point Duration
Rodrigo Becerra 24 months from 01.11.1996
Informatica El Corte Inglés, S.A.
Travesia Costa Brava, 4
28034 MADRID (Spain) tel: +34 1 387 47 00
fax: +34 1 734 47 76
EP 23222 NEW EMPHASIS
Enhanced Mobile Phone with Application Specific Memory System Summary
The aim of the project is the development of an application specific memory integrating flash and EEPROM functions on the same chip for use, amongst others, in cellular phone applications. This innovative semiconductor device will be developed by the semiconductor company, SGS-Thomson, to the specifications determined by cellular phone manufacturer Nokia who will include the device in a phone demonstrator. Characterisation and process reliability studies will be undertaken at the IMEL research institute.
A new non-volatile memory cell concept will be developed in order to integrate both flash and EEPROM memory structures on the same chip without any increase in manufacturing complexity.
The main objective of the project is to deliver a full featured 1.8GHz GSM phone incorporating a prototype of the integrated embedded applications specific memory system developed in the project. The prototype phone will be tested with the Nokia standard validation procedure which includes, amongst others, durability testing at high and low temperatures;
The application specific memory will be initially manufactured in 0.6 µm technology and be shrinkable to 0.5 µm.
The successful completion of the project will provide the opportunity for SGS-Thomson customers to have developed application specific memories combining customisable quantities of flash and EEPROM function for use in a very broad range of market sectors.
SGS-Thomson (I), Nokia NMP (SF), SGS-Thomson (F), Imel (GR)
Contact Point Duration
The COCLICO project aims at the development of an interoperable bi-compatible contact/contactless Smart Card system based on a secure single chip microcontroller. The main target application is a combined Transport Ticketing and Electronic Payment card. The COCLICO project will develop a Smart Card System that combines ISO7816 contact with “remote coupling” (10 cm distance) contactless operation.
The COCLICO microcontroller IC and its tailored microcode will provide the high security level required for banking applications, with the necessary programmable flexibility to adapt the security algorithms to national regulations or specific application needs. It will also feature the contactless operation required for public transport ticketing applications with a fast transaction time.
The COCLICO terminal interface IC and its associated control software will assure Card-to-Terminal and Terminal-to-Card compatibility established in this system specification for contactless operation.
· Specification and performance that meet world-wide market needs and standards
· R&D and design of a contactless/contact secure microcontroller chip
· R&D and design of a companion terminal Interface chip
· Development of a cost effective Smart Card assembly process
· Break-through in low-cost Terminal architecture
Stable and secure microcode for the contactless functions of the Smart Card and Terminal Subsystem
Scientific contributions to the emerging ISO 14443 standard for contactless type 2 systems
Gemplus (F), Motorola (CH, UK, F), Amex (UK), Sistema 4b (E)
Contact Point Duration