Ep optima synopsis

Summary

The IN-RAM project (INtelligent RAM component for streaming applications) is aimed at providing a high performance IC component, optimized for interfacing and buffering multiple high bandwidth streaming data (e.g. video streams, high speed telecommunication data, computer I/O, etc.). Based on the features of IN-RAM and the resulting simplifications in system design, it is expected that commercial realizations of IN-RAM will capture a significant market share in the area of custom memory and interface components.

Moreover, IN-RAM plans to improve the current state-of-the-art in building efficient technology to incorporate large regular structures (DRAM) together with complex high speed logic in a way that minimizes die size as well as manufacturing cost. The focus regarding this objective is not only in the VLSI manufacturing process, but also in the design approach and the utilized CAE tools.

The IN-RAM approach will offer the following innovative characteristics:

i) Integrated single chip solution, manufactured using state of the art VLSI technology.

ii) A scaleable IN-RAM architecture will lead to the development of a family of IN-RAM compliant components.

The project developments will be supported by a complete exploitation roadmap by the industrial partners and in particular by the semiconductor vendor (SGS Thomson).

Objectives

• 
  Design and develop a highly competitive IN-RAM component, using state of the art tools and technology.
  
• 
  Define the overall specifications and architecture of the IN-RAM component based on the requirements of potential users and applications.
  
• 
  Minimize the development risk of the component. This goal will be pursued mainly during design time, investigating implementation alternatives.
  
• 
  Demonstrate the feasibility and usability of the component by embedding it into high performance subsystems. The IN-RAM component’s capabilities will be verified and demonstrated within the project. The IN-RAM component will be integrated in two application systems.
  

Participants

Italtel (I), Intracom (GR), NTUA (GR), SGS-Thomson (I), Solinet (D)

Contact Point Luigi Verri Italtel, Central R&D Palazzo Laboratori, C02 I-20019 Settimo Milanese (Italy) tel.: [phone] fax.: [phone] E-mail: [e-mail]

Duration 24 months from 1.1.1998

EP 21570 AUDICO

Multi-chip Module Automotive Digital Core for Electronics Control Unit
Summary

A low cost existing MCM technology, based on laminated substrate (MCM-L) has been developed for telecom and computer applications. The main content of the work will consist in adapting this technology to meet automotive harsh environment requirements. The packaging and assembly techniques will be exploited to the high volumes series.

Other topics addressed in this project include reliability, testability, modelling (thermomechanical and power dissipation) and implementation of a KGD technology for automotive cost and reliability requirements. Integration of passive components and MCM compatibility with insulated Metallic Substrate (Automotive Mother Board Substrate) are critical issues which are also addressed by AUDICO. The demonstration of this approach will be achieved by realising the digital core of an Electronic Control Unit including microprocessor, associated memory and the interface circuit.
Objectives

· To make available MCM technologies for automotive subsystems in order to solve the integration problem common to future electronics automotive systems with cost efficiency.

· To transfer the results of the programme into production on a short time-scale.
· To open Known Good Die availability in a flip chip configuration.
Participants

Sagem (F); Rover (UK); Bull (F); Motorola (D); tu-b (D).
Contact Point Duration

Jean-Paul Rouet 24 months from 01.02.96

SAGEM SA

27 rue Leblanc

75512 Paris Cedex 15 (France)
tel: [phone]

fax: [phone]

EP 21807 MEDID

Microelectronics for Large Area, High Resolution, Real-Time, Flat, Digital Image Detectors
Summary

Professional markets (medical, factory automation, etc.) have increasing need for real-time direct digital image sensors, of large area, small thickness, high resolution and high reliability, for operation in specific environments. Present sensors do not meet all these requirements.

MEDID aims to develop a high sensitivity flat panel detector prototype of large area (~40x40 cm), high resolution (pixel pitch ~ 140 micron) and high image processing capability (> 1 GOPS). The detector will meet user/end-user needs for digital real-time radiography, including the high reliability and endurance required by medical and industrial environments. This detector subsystem will allow significant application innovation including the possibility of radiological film substitution, lower irradiation dose and exploitation costs, and immediate electronic image availability.
Objectives

· The proposed high resolution detector subsystem will build on existing expertise and prototypes. It will be based on an active matrix sensor where each pixel is made of thin film amorphous silicon photodiodes acting as sensitive elements coupled to switching diodes. Silicon Sensor Panel Technology taking advantage of microelectronic technologies is actually the best candidate to fulfil advanced real-time digital imaging requirements with cost-effective solutions.

· High data volume/real-time pre-processing electronics will be also developed. These components will be integrated in a digital detector which will be tested under working conditions to meet application needs.
· Marketing of the resulting detector is expected within one year after project completion.
Results after one year

Design is complete and full size prototypes are in progress. A small demonstrator provides a high quality radiological image.

Participants

Thomson Tubes Electronics (F); Siemens (D)
Contact Point Duration

J. Chabbal 24 months from 01.03.96

Thomson Tubes Electronics

18, Avenue du Maréchal Juin

92366 MEUDON LA FORÊT (France)
tel: [phone]

fax: [phone]

EP 23199 HIPOCRAT
Human implantable prosthesis offering cardiac rhythm assistance therapy
Summary

The project is aiming to develop a miniature low power hybrid circuit devoted to human implantable cardiac prostheses (pacemakers and defibrillators) which are light weight, highly reliable, battery powered systems. A family of three integrated circuits using the most advanced technologies based on submicronic mixed ANALOG/DIGITAL BiCMOS and HIGH VOLTAGE protection processes will be designed. The size reduction is achieved implementing a plastic chip scale packaging process.

Objectives

• 
  Design of a complete highly reliable, low power, hybrid electronic circuit implying the development of three ASICs and a substrate encompassing the packaged dies and required external components. Two ASICs will be designed using low voltage "BiCMOS5" process from ST: a mixed chip integrating all the specific prostheses functions and a 8 bit microcontroller with fast telemetry function. A protection and interface circuit will be realised using the high voltage "CBZ" process from AMS.
  
• 
  Adaptation of 0.5µm BiCMOS process design kit:
  

new devices generators and cells in MENTOR GRAPHICS environment;

characterisation of the digital library at 1.5V instead of 3.3V for low power design.

• 
  Integration of the high voltage "CBZ" process in MENTOR GRAPHICS environment with specific devices and adaptation to low power requirements.
  
• 
  Implementation of a chip scale plastic packaging at wafer level suitable for ASICs and silicon microsensors.
  

Participants
ELA Medical (F); SGS-Thomson (F); AMS (A); Syndesis (GR)
Contact Point Duration

Thierry Legay 24 months from 01.10.96

ELA RECHERCHE

Centre d'Affaires La Boursidière

92357 LE PLESSIS ROBINSON (France)
tel: + 33 1 46013457

fax: + 33 1 46013355

E-mail: [e-mail]

EP 24359 ROBAS

ROBust ASICs for automotive
Summary

Increased functionality in automotive safety, performance/economy, and comfort requires an ever increasing electronic content in modern motor vehicles. Additionally bus-wiring systems and increase integration level often push the electronic functionality temperature, humidity and electrical disturbance signals.

On the other hand customers demand improved reliability, with component failure rates at the ppm level, simultaneously with the increased complexity.

ROBAS addresses the issue of improved reliability in the hostile environment and describes improvements at all levels in the ASIC design and manufacturing chain.

Objectives

· ROBAS partners will further “ruggedise” automotive ASICs with regard to handling and use, by improving ASIC specification and actual performance in the areas of ESD protection, sensitivity and emission of Electromagnetic Disturbances (EMC) and in-silicon disturbances by substrate coupling and transmission effects.

· Reliability levels of less than 10ppm failures without expensive burn-in screening will be sought by “designing-in” and “building-in” reliability with such measures as wafer-level-reliability (WLR) practised in manufacturing and improved fault simulation and built-in test features during design.
· Operation and performance at increased ambient temperature, form the present 85°C up to 135°C will be targeted and implemented.
· Two robust ASIC demonstrators will be developed to demonstrate the improvements achieved by the project. These will be a radio-security-key and a general purpose chassis ASIC with µP core for security applications.
Participants

Lucas Automotive (UK), BMW (D), Land-Rover (UK), Elmos (D), Dolphin Integration (F), PES (D)
Contact Point Duration

Ms Gail Perrins 24 months from 15.01. 97

LUCAS

Windrush Park Road

Witney

OX8 5EX OXON (United Kingdom)
tel: [phone]

fax: [phone]

E-mail: [e-mail]

EP 21227 OSIM-CHIPSET

Open and Scaleable Intelligent Metering System Chipset
Summary

The chipset developed in the OSIM chipset project will provide a cost effective way of implementing communication between the electricity utilities and their customers. This project will run in close cooperation with the OSIM AHSII project that treats the development of equipment for the communication gateway. The project includes the development of three integrated circuits namely the Power Line Carrier Modem, the line driver and a generalised interface to a metering device.

Objectives

The project is aimed at the development of a chipset that will consist of three devices:

· The PLC Modem

This modem chip formats data sent or received via the power line. The modulation type is Spread-Frequency Shift Key in the 50 kHz to 100 kHz frequency band, with a baud rate of 1200 baud. The protocol will be handled via an external microprocessor. Frame synchronisation, deframing and error correction will be done internally by embedded logic. It will comply with the Cenelec standards EN 500651.

· The Metering Device Interface

Will provide the electrical interface with the electricity, gas, water and heat meters within the cost constraints. It has to fulfil the major standards IEC 1107, IEC 1142 and DIN 43.864 or 50 interface. The circuit should also contain the necessary driver, signal conditioning circuitry and protection against disturbances.

· The Driver Circuit

Will provide the high driving current (250 mA) and signal conditioning of the output and input signals such as amplitude limiting and AGC for the input signals.

Participants

Alcatel Mietec (B); Landis & Gyr (CH); Alcatel SESA (E)
Contact Point Duration

dr. Edmond Janssens 24 months from 01.01.96

Alcatel Mietec

Westerring 15

9700 Oudenaarde (Belgium)
tel: [phone]

fax: [phone]

E-mail: [e-mail]

EP 23224 PROXIMA

Programmable Maximum Integrated Electronic Trip

Summary

Actuator trip units of an electricity circuit power breaker suffer from lack of accuracy which limits their installation and exploitation. The use of electronic actuator trip units consisting of a single mixed mode ASIC would not only allow an economical implementation of the required accuracy, it would also allow additional functionality such as programmability for greater flexibility and remote monitoring of individual loads via the EMS TP0 Home Systems Communication interface.

The biggest challenge for the circuit is the design of a high sensitivity front end for equipment that switches currents of several thousands of amperes.
Objectives

· To realise an electronic trip unit based on a single ASIC with the following specification

- current range 200A to 200 000A

- 0.1% relative accuracy

- fully compliant with EMC, mechanical and climatic standards

- protection modes: instantaneous, short time, long time, ground fault.

· To develop an ASIC that contains the analogue interface for the trip unit and includes the required functionality.
· To design an analogue front end with 12 bit accuracy and low offset 50-100µV.

Participants

Alcatel Mietec (B), Schneider Electric (F)
Contact Point Duration

dr Edmond Janssens 24 months from 01.10.96

Alcatel Mietec

Westerring 15

B 9700 Oudenaarde (Belgium)
Tel: [phone]

Fax: [phone]

E-mail: [e-mail]
EP 24315 SCARF

Smart Communicating Applications using Radio Frequency
Summary

A low-cost, single-chip RF IC transceiver suitable for consumer as well as industrial and commercial applications is to be developed. This component will be accompanied by development tools (in the form of ready-to-use demonstration circuits and software libraries for standard microcontrollers) enabling the development, testing and validation of low power RF applications. The component will be integrated and validated in a commercial application, Automatic Meter Reading, and will demonstrate its viability in the domain of Home Systems in the process. The goal is to reduce the cost and performance barriers to the mass scale implementation of low-power RF applications.

Objectives

• 
  A highly-integrated, low-cost bidirectional RF transceiver developed using an advanced BiCMOS4 technology, ensuring low power consumption and operation at high frequency.
  

• 
  Tools for RF hardware and application design in the form of development kits and software libraries for a range of microcontrollers.
  

• 
  Equipment and methods for conformance testing in accordance with established standards, to ensure that the RF medium and resulting applications developed on the basis of the RFIC conform with established norms.
  

• 
  A commercial application utilising the new RFIC as its hardware base and providing a means to automate meter reading in the utility industries (electricity, gas, water and heat) and entry into the Home Automation (HA) segments in Europe.
  

Participants

Itron SA (F); SGS-THOMSON Microelectronics (F); Trialog SA (F); Itron Ltd (UK); University of Bristol (Centre for Communications Research) (UK).
Contact Point Duration

Joseph Grant 24 months from 06.01.97

Itron SA

Immeuble Merblanc

1, rue du Port au Prince

F-38200 Vienne (France)
tel: [phone]

fax: [phone]

E-mail: [e-mail]
EP 20508 LAYSYN

Physical Design Synthesis
Summary

The challenges of high density, complex circuitry and the demands of new substrate and packaging technologies impose progressively greater pressures on PCB and MCM designers. In addition, the pressure to reduce time-to-market is a constant requirement. These demands require new developments in CAD tools to allow designers not only to take into account a huge set of constraints imposed by circuit speed, manufacturing requirements, thermal performance, and the specifications of reliability and EM interference, but also to perform the design function in shorter time frames on the way to achieving complete design "compilation" or "synthesis".

Objectives

· To provide tools which support the effective design of PCB/MCMs using current and newly emerging technologies.

· To provide a unified environment in which the placement and routing activities can be considered together, with constraints and design rules from either discipline being obeyed simultaneously.
· To increase the productivity of PCB/MCM designers to allow demands of decreasing time to market targets to be met.
· The project will validate the tools and work practices in commercial design environments. The users are committed to using the tools developed on real production designs and, if successful, to adopt them into their design departments.
· The results will be progressively delivered to the market by the EDA vendor partner.
Participants

Zuken Redac (UK); ICL (UK); Thomson multimedia (F); Bull (F), SNI (D).
Contact Point Duration

Roy Davies 36 months from 02.01.96

Redac Systems Ltd.

Green Lane

Tewkesbury

GLOS GL20 8HE (United Kingdom)
tel: [phone]

fax: [phone]

E-mail: [e-mail]

EP 21261 AMITY

Analogue/Mixed-Signal Sub-Micron
Design Test Bench System
Summary

The software tools and methods developed in the project will be defined in a close collaboration between a leading mixed-signal application user company in the automotive and communications electronics sector (Robert Bosch GmbH) and a leading vendor in mixed-signal design verification (MicroLEX Systems A/S). The toolset developed will include software (virtual) instrumentation for the verification and test of mixed-signal ASICs and will be presented and accessible through a user friendly engineering interface. The project will focus on the development of a number of specific automotive and communications systems tools, however, the use of virtual instrumentation methods will enable rapid adaptation of the solutions to suit related circuit functions.

Objectives

· The objectives of the project are to develop and demonstrate innovative analogue and mixed-signal test techniques and tools including novel implementations of advanced algorithms for digital signal processing type testing.

· The project will assess the viability of alternative methodologies and tools for analogue and mixed-signal test and verification of CMOS and bipolar technologies, in particular for sub-micron CMOS based ICs and subsystems.
· The first set of solutions will be focused on circuit structures typically found in automotive and communication electronics.
· A ß-release of the design test-bench tools will take place during the project and ß type testing of these prototype tools will be undertaken using several in-house electronic subsystem demonstrators.
· The project results will form the basis for a commercial release of the tools after the end of the project.
Participants

Robert Bosch GmbH (D); MicroLEX Systems A/S (DK).
Contact Point Duration

Dr. Wilfried Tenten 34 months from 01.12.95

Robert Bosch GmbH

K8/EIS2 Postfach 13 42
72703 Reutlingen (Germany)
tel: [phone]

fax: [phone]

E-mail: [e-mail]

EP 21404 EDGE

Enhanced Design for GaAs/Si in Europe
Summary

The overall objective of EDGE is to provide a new, user-oriented and commercially-driven CAD resource to support high-frequency analogue design in Europe, specifically targeting linear and non-linear MMICs, as well as interconnect structures, for operation from 0.1 GHz to 100 GHz and beyond. The project’s main outside industrial impact will be through enabling shorter time-to-market and reduced cost for successful circuit realisation in several key application sectors with major growth potential in the microwave, RF and mm-wave area, especially those related to Si- and GaAs-based components for wireless communications.

Objectives

· Demonstration of effective, working, user-friendly links between existing different European CAD tools, to be exploited commercially as new product enhancements.

 The project will allow users to complement their existing investments in CAD products from US vendors (in particular from HP-EEsof) with a set of easy-to-use extensions and links to European CAD tools/models offering added user value.
 Major enhancements to existing CAD interface formats will be demonstrated through the provision of direct access to MMIC foundry library modules. Furthermore, the consortium intend to work towards a common European style of user interface.
 New analysis techniques will be provided for MMICs which are complex, multi-function and operating in strongly non-linear and/or low-power regimes.
 An advanced, standardised, non-linear FET model will be delivered for at least two of the foundry processes represented in the consortium, using a synthesis of the best available research ideas, including a unified, physics-constrained model.
Participants

UCD (IRL); BML (UK); Dassault Electronique (F); GaAsCode (UK); GMMT (UK); Jansen Microwave GmbH (D); PML (F); Univ. of Rome II (I).
Contact Point Duration

Thomas J. Brazil 24 months from 15.03.96

Department of Electronic Engineering

University College Dublin

DUBLIN 4 (Ireland)
tel: [phone]

fax: [phone]

E-mail: [e-mail]

EP 21625 FIPSOC

Field Programmable System on Chip
Summary

The aim is to develop the first member of a family of Field Programmable System-On-a-Chip (FIPSOC) devices. These circuits will integrate combinational logic blocks, programmable analogue cells for signal conditioning and data acquisition, and an on-board microprocessor. Configuration and control data will be stored in on-chip RAM memory. The on-board 8051 based microprocessor will be able to access both the configuration and the actual signals within the logic cells, providing a strong interaction between hardware and software. Standard, off-the-shelf FIPSOC devices will be configurable to a wide variety of tasks including analogue and digital data acquisition and processing as typically required by the electronic instrumentation and industrial process control sectors. Users can develop their own applications by implementing (programming) both hardware and software functions in the same device. The chip will be ideally suited as an easy-to-use system prototyping workbench as well as in low to medium volume product applications.

Objectives

· To develop a set of programmable analogue cells and routing resources. Cells will include analogue interfaces, DACs and ADC, amplifiers, filters. This function library will include a bridge to commercial standard-cell libraries to enable migration from programmed FIPSOC prototypes to classical ASIC solutions in case of large production volumes.

· The project will develop the first member of the FIPSOC family in a 0.5 micron CMOS process. It will integrate analogue functionality, ~5k programmable digital gates, an 8051 based microprocessor core, and programme/control memory.

· The project will develop a software toolkit to enable programming of both digital and analogue functionality as well as data processing and control functions undertaken by the on-board microprocessor. The toolkit will be PC based and include schematic capture, routing and chip interface capture and design functions.

· In order to demonstrate versatility, level of system integration and performance, the partners will use FIPSOC-1 in a number of industrial demonstrators including a coin recogniser for vending machines and a smart battery charger.