Ep optima synopsis

Participants

Toucan Technology Ltd (IRL)
Contact Point Duration

Aedan Coffey 12 months from 15.03.96

Toucan Technology Ltd

Galway Technology Centre

Mervue Industrial Estate,

Galway (Ireland)
tel: [phone]

fax: [phone]

E-mail: [e-mail]

EP 22342 VSDSE

VHDL-based System Design and Simulation Environment
Summary

In this Application Experiment a hardware design environment for hardware is to be established for complex PLDs as well as ASICs and PCBs using the same advanced top-down methodology, the same tools and similar flows in the system design before the implementation phase. VHDL which is an international standard was selected to form the basis of the work to be done. The design environment planned will enable us to perform VHDL-based board and system simulations in an early stage of product development.

Objectives

· A model of the system under design is to be created before the implementation phase by using only VHDL models and a special component library (SmartModels).

· Verification of the functionality of the new system design is to be done only by using a VHDL simulator and component libraries (VHDL and SmartModels). No traditional gate simulator will be used.
· Special methods are to be introduced into the system testbench for automating the simulation process and result analysis and therefore improving the efficiency of development work.
· Design risks will be minimised, as decisions on architecture can be verified in a rather early stage of the design process.
· An earlier failure detection and shorter iteration loops will lead to shorter design periods.
 Verification of functional operability of the system to be designed by simulation will reduce the time needed for putting it into operation.
Participants

SNAT (D).
Contact Point Duration

Michael Szengel 15 months from 15.03.96

Siemens Nixdorf Advanced Technologies GmbH

Scharfenberger Straße 66

D-001139 Dresden (Germany)
tel: [phone]

fax: [phone]

E-mail: [e-mail]

EP 22408 ECU

Design and Product Development of New Generation of ECU
Summary

Products designed for automotive applications must undergo an extensive and time consuming testing program. This, together with the relative short life of the vehicle models, imposes a number of constraints on the length of time allowed between the conception of the idea and the starting of the production activity.

The objective of this Application Experiment is to reduce the concept-to-market time introducing a design methodology which allows the designer to test and verify his work as early as possible in the design process. The standards of quality, reliability, performance, and cost can be attained only if the products are designed, from the very beginning, with these objectives in mind.
Objectives

· Reduction of time to market

· Reduction of product development costs
· Introduction of new technologies
Participants__TRINAMIC_Electronic_System_Design_GmbH_(D)_Contact_Point_Duration'>Participants

Magneti Marelli S.p.A. (I).
Contact Point Duration

Maurizio Catena 16 months from 17.06.96
MAGNETI MARELLI Electronics Division
Viale Carlo Emanuele II, 118
10078 VENARIA REALE (TORINO) (Italy)
tel: [phone]

fax: [phone]

E-mail: [e-mail]

EP 22818 MCC

Design of Motion Control Chip
Summary

The Application Experiment is TRINAMIC’s entry into the field of ASIC design. TRINAMIC’s know-how from the development of a range of microcontroller based stepper motor controllers will be used to design an advanced single chip stepper motor controller (MCC). The MCC will be implemented as an ASIC in co-operation with the University of Hamburg using state-of-the-art Cadence DFW-II chip development tool chain which has been in use at the university for several years.

Objectives

· Acquisition of knowledge in VHDL standard language for hardware specification, synthesis and documentation.

· Reduction of design time from between 6 to 30 weeks down to 2 to 10 weeks.
· Improved testability reducing failure rate to 25% of current value
· Improved reliability and functionality together with 20% reduction in cost.
Participants

TRINAMIC Electronic System Design GmbH (D)
Contact Point Duration

Dr Michael Randt 12 months from 01.10.96
TRIANAMIC Electronic System Design GmbH
Preystrasse 14
D-22303 HAMBURG (Germany)
tel: [phone]

fax: [phone]

E-mail:[e-mail]

EP 23051 VMUSB

VHDL Model of Universal Serial Bus to ISA Bus Adapter

Summary

This Application Experiment will lead to improved design methodologies and personal skills equivalent to the current state-of-the-art techniques. These will be achieved during the course of developing a VHDL model of a universal serial bus to industry standard architecture bus interface. The main result will be new skills in VHDL and analogue design methodologies plus an improved product. This will enable the company to maintain its market edge as a producer of single chip solutions for computer peripheral interfaces.

Objectives

· Acquisition of a library of components some 50% of which would be re-usable in future designs.

· A reduction of 50% in design time which is currently taking 4 to 5 months.
· A 25% reduction in the time-to-market currently running at 6 to 8 months.
Participants

Shuttle Technology Ltd (UK)
Contact Point Duration

David Bradley 12 months from 15.08.96
Shuttle Technology Ltd
Alba House, Mulberry Business Park
Wokingham RG41 2GY, (United Kingdom)
tel: [phone]

fax: [phone]

E-mail:[e-mail]

EP 23104 CATG

Coverage Analysis and Test Generation
Summary

This Application Experiment will measurably improve the efficiency and quality of functional fault coverage of highly complex systems on Silicon. The VHDL Cover tool will be integrated into the existing design flow. The tool will be exercised and evaluated during application to the design of the Chameleon family of 64-bit microprocessors offering highly integrated software-based solutions thereby supporting flexibility in the end application.

Functional verification is estimated to take between 30 and 50% of the design resource for typical microprocessor development. The expected impact from the experiment will be improvements in the efficiency and quality of functional coverage of these highly complex systems on Silicon.

Objectives

· Reduction of manual overhead in coverage analysis to 25% of its current value.

· Reduction of machine time to perform VHDL statement coverage to 75% of current value.
· Add ability to generate branch, condition, path triggering and signal coverage to existing ability.
Participants__Snaketech_(F)'>Participants

SGS-Thomson Microelectronics Ltd (UK)
Contact Point Duration

Michael Bartley 12 months from 28.11.96
SGS-Thomson Microelectronics Ltd
Aztec West 1000
BS12 4SQ BRISTOL, (United Kingdom)
tel: [phone]

fax: [phone]

E-mail:[e-mail]

EP 23181 OSSWLAN

Optimized Spread Spectrum Wireless - LAN
Summary

The main objective of this project is the experimental use of state-of-the-art design tools in order to upgrade and enhance the electronics and ASIC design process, and more specifically to re-design a WLAN transceiver.

Objectives

· STS expects the project to result in a reduction of design time, time-to-market and the cost of design as well as an improvement of quality in terms of increased effectiveness and decreased faults/defects. At the same time, the adoption of advanced design tools is expected to offer STS staff members the opportunity to gain useful experience with the help of such electronic development tools.

· The anticipated impact of the experimental project in question is that STS, as “idea and prototype factory”, will become capable of a more rapid and effective/efficient realisation of ideas, which will benefit STS considerably. In commercial terms, one could argue that the ability to demonstrate a simulation at an earlier stage of development will make it more likely to attract, convince, inspire confidence in potential clients, production and marketing partners and in doing so achieve their business commitment.
· Dissemination of the project’s results to a wider community will take place in various ways, i.e. contribution to national and international workshops, participation in presentations and preparation of articles for international / European magazines.
Participants__Technical_University_of_DELFT/_DIMES_(NL)'>Participants

STS-Smart Telecom Solutions (NL)
Contact Point Duration

Hans van Leeuwen 12 months from 01.10.96

STS-Smart Telecom Solutions

Keizersgracht 298

NL - 1016 EW AMSTERDAM (The Netherlands)
tel: [phone]

fax: [phone]

E-mail: [e-mail]

EP 23237 CORE

Core Processor Implementation for ADSL Telecom Applications
Summary

The main objective of the action is to investigate and do a feasibility on the improved utilisation of state-of-the-art tools (i.e. Virtuoso tools from Eonic Systems) to allow run-time support with core microprocessors for HW/SW codesign system-on-silicon implementations.

Objectives

· Expected results: real-time operating system tools are nowadays usually applied for software implementations on fixed pre-defined board level architectures. The main result that can be expected of this project will be the proof that these functionalities can be used as well for HW/SW co-designs making use of embedded cores (e.g. ARM7), and that they can be encapsulated in a global system design and synthesis flow.

· Expected impact of results: the major impact of the project results will be that the utilisation of the Virtuoso run-time support tools with ultra-fast switching times can be extended from software implementations on fixed pre-defined board level architectures towards HW/SM co-designs with embedded cores (ARM7 in this project). This will allow other users to benefit from the establishments. For the user company itself, the feasibility study in this project can lead to an improved design efficiency and a higher design quality, for the ADSL application specifically but also for future applications.
· Participation and contribution to open international workshops and/or conferences in the target area will be planned, at mid-term and at completion of the project period, to transfer the expertise and benefits of this project to other companies. Actions will be prepared by the tool vendor to facilitate the usage of their tools in future design flows, and to disseminate the expertise gained from this application experiment through their commercial contracts with other European companies. Since the activities of this project are really innovative but in line with the major trends in electronic system design, the potential for replication of the outcome of this project to other companies will be sufficiently high, and new research activities can be started-up.
Participants

Alcatel Bell (B)
Contact Point Duration

Marc Genoe 12 months from 01.10.96

Alcatel Bell N.V. Microelectronics

F. Wellesplein 1

B-2018 ANTWERPEN (Belgium)
tel: [phone]

fax: [phone]

E-mail: [e-mail]

EP 25558 PASCALE

Parasitic Substrate Coupling Analysis by Layout Extraction

Summary

The principle objective of the project is to contribute to better predictability of IC behaviour and hence reduce the number of re-design iterations due to substrate coupling by providing an industrial computer substrate coupling modelling and analysis software to semiconductor companies.

This project will contribute to the development, intensive test and enhancement of LAYIN, a complete CAD package designated to parameterizing, modelling and analysing parasitic crosstalk related to the substrate of integrated circuits. Starting from a functional netlist, from the IC layout and from a description of the technology, the software extracts the parasitic substrate model of the IC, completes the simulation data files, and displays the substrate noise distribution. It will include a parameterization tool to create technology descriptions from actual fabrication process data.

Objectives

• 
  Development of a Technology Characterization Tool (TCT) to generate the technology description from fabrication process data via Graphic User Interface (GUI).
  
• 
  GUI dedicated to the pre- and post-processing of the data required by the stand-alone tools. The GUI, initially developed as a stand-alone tool, will be integrated into the Layout Editor of Cadence Design Systems.
  
• 
  Stand-alone UNIX tool to extract a surface model of the substrate necessary to visualise noise distributions, as well as a macromodel compatible with SPICE and ELDO simulators.
  
• 
  Stand-alone UNIX tool to generate CIF representations of substrate noise distributions from surface models.
  
• 
  Development and test of dedicated demonstrators and test cases by the Users.
  

Participants

Snaketech (F), Atmel ES2 (F), C.I.S.S. (A), EPFL (CH), Ericsson (S), GEC-Plessey (UK), SGS-Thomson (F)
Contact Point Duration

Michel Oger, 18 months from 01.07.97

Snake Technologies s.a.r.l

Place de la Chaffardière,

F-38620 , St Geoire en Valdaine, (France)
Tel: [phone]

Fax: [phone]

E-mail: [e-mail]

EP 26698 SIFGEN

Software Interface Function Generator
Summary

The project will deliver an improved method, with supporting tools, for the development of low level embedded software. By using advanced automatic code generation techniques to produce all low level, hardware related functions, the programmer can significantly reduce development time.

The tools shall provide the user with intelligent support, providing the capability to quickly and accurately enter all of the programmable information associated with a given embedded microprocessor system. From this database of information the user shall then be able to automatically generate a library of low level Software Interface Functions (SIFs), designated Level 1 SIFs, which constitute a uniform layer of abstraction away from the embedded system hardware. This Level 1 SIF layer provides a clean interface on top of which system software can be built.

In addition, the tools shall also provide the user with the capability to combine Level 1 SIFs, to form Level 2 SIFs, thus providing yet another layer of software abstraction from the hardware system.

To improve the process of writing software, the libraries of Level 1 & 2 SIFs will be accessible to the user via a text editor, for direct placement into a source code program.
Objectives

· Develop a method for rapidly developing low level embedded software.

· Provide a suite of intelligent tools to support the method.

· Demonstrate the tools in operation.

· Reduce user development time & effort for low level embedded software.

Participants

GEC-Plessey Semiconductors (UK), Etnoteam (I), R&C (UK)

Contact Point Duration

Colin Tattersall 10 months from 01.01.1998

GEC Plessey Semiconductors

Tamerton Road, Roborough, Plymouth,UK PL6 7BQ

Tel: [phone]

Fax: [phone]

E-mail: [e-mail]

Design Clusters

EP 25213 TARDIS

Design Clusters: Technical Coordination and Dissemination
Summary

The Design Clusters action aims to foster excellence in design skills, and to bring these skills to broad industrial use. Design Clusters are co-ordinated sets of design experiments comprising research and best practice work.

Cluster themes currently addressed are Low Power Design and Mixed Signal Design, co-ordinated by DIMES and CNM respectively. The specific goals are:

Low Power Design: design methods for reducing the power consumption of electronic circuits.

Mixed Signal Design: design methods for solving problems related to integrating analogue and digital functions on a single device.

19 design experiments were launched at the end of 1997; additional experiments are planned. Capturing and dissemination of their gathered knowledge and experience to third parties is organised through the TARDIS project by the cluster co-ordinator with the support of design experiments.

Objectives

· To organise the communication between design experiments and to exploit their potential synergy;

· To guide the capturing of methods and experiences gained in the design experiments;

· To organise and promote the wider dissemination and use of the gathered design know-how and experience.

Participants

Technical University of DELFT/ DIMES (NL), CNM (E), participants of all Design Experiments
Contact Point Duration

Dr. Rene van Leuken, 42 months from 16.07.97

DIMES Design and Test Centre H16 CAS

Mekelweg 4, NL-2628 CD Delft, The Netherlands
Tel: [phone]

Fax: [phone]

E-mail: [e-mail]

Cluster Homepage: http://www.ddtc.dimes.tudelft.nl/ESD-LPD

EP 25242 PREST

Power REduction for System Technologies
Summary

In this programme the partners will study, develop and demonstrate techniques for Low Power / Low voltage IC operation with the aim of reducing typical system power demand by a factor of ten through the application of new circuit design techniques and supply voltage reduction on an advanced bulk CMOS process.

The work will concentrate on the digital circuits identified as the main areas of current consumption in GSM personal communications integrated circuits (specifically the GPS GEM series chip-set) with the aim of raising the mobile phone performance to 1000 hours standby and 10 hours talk time between re-charging. Current systems are achieving around 100 hours standby and 2 to 4 hours talk time depending on the distance from the base station.
Objectives

· Survey and Report on contemporary techniques for Low Power Design

· Survey and Report on commercial power analysis software tools

· Report on Architectural design techniques with a power consumption comparison

· Report on Algorithmic design techniques with a power consumption comparison

· Report on Asynchronous design techniques and Arithmetic styles

· Produce description of low-power design flow

· Fabricate and characterise demonstrator to assess the most promising power reduction techniques

Participants

GEC Plessey Semiconductors (UK), University Of Manchester (UK), Queens University, Belfast (UK) & University Of Sheffield (UK).
Contact Point Duration

Denzil Broadhurst, 24 months from 01.11.97

GEC Plessey Semiconductors

MicroElectronics Centre

Hollinwood, Oldham

OL9 7LA (United Kingdom)
Tel: [phone]

Fax: [phone]

E-mail: [e-mail]

EP 25248 LOVO

Low Output VOltage DC/DC converters for low power applications
Summary

This Design Experiment addresses new design methodologies that will contribute to a significant decrease of power dissipation in electronic equipment by decreasing the power consumption and dissipation of the DC/DC converters feeding low power electronics.

New low power systems mainly require low supply voltage. However, the lower the output voltage the lower the efficiency of the DC/DC converter. This is a very important drawback because size of the power converter is highly dependent on the efficiency, and furthermore, the ratio volume/watt in DC/DC converters is higher and higher as the output voltage is reduced. Therefore, it could be the case that future low power integrated circuits could be really small, and on the contrary the converter that feeds it would be a bulky and inefficient one.

The experiment consists of checking the feasibility of new approaches to design and manufacture DC/DC converters generating very low output voltages (< 3.3 V), required for such applications. The main features are:

• 
  very low output voltage: 1.5 V
  
• 
  output power: 15 W
  
• 
  very high efficiency (>85%) in an industrial application within the Telecommunication sector;
  
• 
  low volume (size lower than 25x25x10 mm³);
  
• 
  low cost (< 10 ECUs).
  

Objectives

• 
  Development of technical solutions for the power supplies of advanced low power systems, comprising the following topics,
  
• 
  New methods for synchronous rectification for very low output voltage power converters;
  
• 
  Analysis of techniques for high density of integration;
  
• 
  Analysis and validation of new components;
  
• 
  Functional demonstrator close to commercial specifications.
  

Participants

Alcatel (E), Universidad Politécnica de Madrid (E)
Contact Point Duration

Enrique de la Cruz 15 months from 01.07.97

Alcatel España S.A.

Ramirez de Prado 5, 28045 Madrid, (Spain)
Tel: [phone]

Fax: [phone]

E-mail: [e-mail]

EP 25249 AMIED

Asynchronous Low-Power Methodology and Implementation of an Encryption/Decryption System
Summary

The aim of the project is the development of a low-power encryption/decryption circuit for data transmission systems. The portability of these systems requires a drastic decrease of their power consumption. The International Data Encryption Algorithm (IDEA) was selected, which is one of the most powerful algorithms today.

A fully asynchronous ASIC implementation of the IDEA algorithm will be developed, which is expected to operate at frequencies up to at least 25 Mbits/sec.

An advanced low-power design flow will be established on the basis of commercially available CAD tools, which can be used also for similar data processing applications. The main effort will be spent on the algorithmic and architectural design levels, with emphasis on asynchronous design methodology.

The reduced power consumption of the asynchronous implementation will be demonstrated by comparison with a synchronous version. It will be tested in two products with different bit rate requirements. Hellenic Aerospace Industries will use the circuits in new versions of their mobile communication products.

The asynchronous design methodology and techniques will be made available to other European companies.

Objectives

· Implementation of the IDEA encryption/decryption method with drastically reduced power consumption;

· Advanced low power design flow with emphasis on algorithm and architecture optimisations;

· Industrial demonstration of the asynchronous design methodology based on commercial tools.