Ep optima synopsis
Contact Point Duration SEA / SEA 300 Office 18 months from 01.01.97
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Contact Point DurationSEA / SEA 300 Office 18 months from 01.01.97Central Microstructure Facility Rutherford Appleton Laboratory Chilton, Didcot, Oxfordshire, OX11 OQX, (United Kingdom) tel: +44 1235 445946 fax: +44 1235 446174 E-mail: sea@rl.ac.uk World Wide Web: http://www.ebl.rl.ac.uk/sea.html EP 25991 FLASH PT 300 Future leadership through assessment of high quality production tool for 300 mm Wafers Summary The project is to assess the Plasmos SD 3000 fully automatic ellipsometer tool for the future 300 mm market and to improve its present performances. The assessment has been organized such that two units are being evaluated at the same time: one to be installed at SELETE, in Yokohama, Japan and a second one, fully automatic, to be installed first at I300I, in Austin, USA, and thereafter at GRESSI to complete the evaluation and implement the improvements. The final outcome of the project will be a reliable 300 mm ellipsometer ready to be used at industrial semiconductor manufacturers facilities for in line control of IC fabrication process on 300 mm silicon wafers. Objectives To measure and evaluate the capabilities for:
Participants: Gressi (F); Plasmos (D); SGS Thomson Microelectronics (F), I300I (USA), SELETE (J) Contact Point Duration Guillermo Bomchil 18 months from 01.07.97 France Telecom Cnet BP 98. 38243 Meylan Cedex France tel: +33 4 76 76 42 22 fax: +33 4 76 90 34 43 E-mail: guillermo.bomchil@cnet.francetelecom.cnet Basic Services and First Users Action EP 21101 EUROPRACTICE BASIC SERVICES Promoting Access to Microelectronics Technologies Summary By incorporating modern microelectronics technologies in their products, companies can enhance production efficiency, reduce cost, improve product performance, reduce size weight and power consumption or gain product differentiation through new functionality. EUROPRACTICE offers a cost-effective and flexible means of accessing ASICs, MCMs and microsystems technologies (MST) with software support and complemented by training and best practice courses; through the provision of consultancy, training, software tools, design support, prototyping, low-volume production runs, packaging and test, and access to “normally” internal volume production facilities. The costs of developing ASICs and MCMs for dedicated applications with low-volume production are often prohibitively high, especially for SMEs. Multi Project Wafer (MPW) runs and dedicated low-volume MCM and MST services offer a cost-effective route to ASIC, MCM and MST design and fabrication. The cost, complexity and expertise required to develop microsystems components or Microsystem based products often present a barrier to the introduction of this technology. Services providing solutions and knowledge in a globally integrated manner including a path from feasibility studies and prototyping through to high volume production are offered. Design, microsystems process technology, as well as packaging and integration of the microsystems component in the final product or system are all covered. EUROPRACTICE Basic Services will reduce the cost and risk for companies who wish to begin using these technologies and for academic institutes who wish to include these technologies in their educational offer. General enquiries may be addressed to the contact point below, from which reference to the best contact for further detailed information may be obtained.
The main instrument for achieving the goals of FUSE is a funded Application Experiment (AE). In these experiments, an enterprise will carry out the design, manufacture and test of a component which is relevant to the improvement of their manufactured products. A vital principle of FUSE is that the participating enterprise acquires the necessary know-how (via collaboration with subcontractors) and experience to access and use microelectronics technologies themselves. The secondary instruments are the Technology Transfer Nodes (TTNs). These nodes are established in regions throughout Europe to provide a local interface to participating enterprises. They proactively seek enterprises in all industry sectors and at all levels of the ‘technology ladder’ and offer technical and economic expertise to assist them in their selection and application of technologies. In addition to the benefits gained by the funded enterprise, FUSE aims to capture and disseminate the essentials of AEs to encourage other enterprises to adopt microelectronics technologies as a means of improving competitiveness. It is the task of the TTNs to extract the essentials of the AEs which they monitor, and use these in order to create awareness of the benefits of microelectronics technologies. Objectives
Participants A European-wide network comprising the TTNs and more than 400 enterprises, most of which are SMEs which participate in Application Experiments . Contact Point Duration Mohamed Wahab 36 months from 01.01.96 University of Glamorgan Mid Glamorgan UK-Pontypridd (United Kingdom) tel: +44 1443 482542 fax: +44 1443 482541 Email: mawahab@glamorgan.ac.uk Networks and Working Groups EP 21949 ACiD-WG Working Group on Asynchronous Circuit Design Summary ACiD-WG coordinates research, training and dissemination activities in Europe concerned with the design of asynchronous digital VLSI circuits. Demonstrator chips, such as those designed on OMI/EXACT (EP6413) and OMI/DE-ARM (EP6909), indicate that asynchronous circuit techniques can help reduce power consumption and electromagnetic radiation. Current sister-projects include OMI/DE2 (EP20452), PREST (EP25242), AMIED (EP25249) and DESCALE (EP25519). The ACiD-WG Technical Management Committee (TMC) consists of ten distinguished European Scientists who have applied their expertise in the fields of computer architecture, DSP, silicon compilation, logic synthesis and formal methods, to the asynchronous domain. European companies are encouraged to becomes ACiD-WG Industrial Affilates.
· Facilitate research and technology transfer activities undertaken by the TMC · Organise European workshops for regular exchange of information and discussion between research teams and industry. · Organise a European summer school aimed at university students, young researchers and practising engineers. · Sponsorship of Async97 and Async99, International Symposia on Advanced Research in Asynchronous Circuits and Systems.
Participants South Bank University (UK); Philips Research Laboratories (NL); Telecom Bretagne (F); Poly. of Catalonia (E); Univ. of Groningen (NL); Univ. of Manchester (UK); Poly. of Turin (I); Eindhoven Univ. of Tec. (NL); Tech. Univ. of Denmark (DK); Univ. of Newcastle upon Tyne (UK). Contact Point Duration Dr. Mark B. Josephs 36 months from 01.05.96 Centre for Concurrent Systems and VLSI School of CISM, South Bank University 103 Borough Road, London SE1 0AA, UK Voice +44 171 815 7413 Fax +44 171 815 7499 Email Mark.Josephs@sbu.ac.uk URL http://www.scism.sbu.ac.uk/ccsv/ACiD-WG EP 20796 GOOD-DIE NETWORK Get Organised Our Dissemination of Die Information in Europe Summary The current acceleration of MCM development is led by the need in electronics packaging for increased integration, reduced size and weight, increased reliability, reduced cost and increased performance. One of the major factors in MCM design is the use of new technology and very high I/O ICs such as microprocessors and ASICs with many thousands of gates. For memories and other devices, the technology is shrinking to 0.5, 0.35 and even 0.25 micron. The use of these new technologies affects the device yield; the higher the number of die per MCM, the greater the risk of low first time yield and the need to rework. In order that the manufacture of these high density MCM electronic modules be cost-competitive with current electronic manufacturing technology, Known Good Die, KGD sourcing must be possible. If the KGD concept is accepted internationally, it will also reduce the costs of single die packaging due to the higher yield of the die. To assist in achieving these requirements, this project is set up to create an information exchange network open to all semiconductor manufacturers, systems designers, MCM manufacturers and users, CAD vendors, standards organisations, etc. for the exchange of information on KGD. This will be based at a technical organisation who will assist in the organisation of seminars, workshops, task forces, a newsletter etc. as the knowledge base for KGD. (See also EP 20797 GOOD-DIE.)
· Create a network with an open membership list. · Set up a programme of meetings, seminars, etc. for information exchange. · Give presentations at other conferences, seminars, etc. on KGD information. · Make contacts with other MCM and electronic packaging groups, e.g. EUROPRACTICE-MCM, NETPACK, JESSI, MCC etc. · Issue a newsletter on KGD and associated topics. · Create contacts made with standards groups to maintain continuity. · Exploit the need for KGD and the use of the databases. Participants Codus (UK), IMEC (B), Philips (CH), Eltek (UK), Rood Technology (NL) Contact Point Duration Mike G. Roughton 30 months from 01.12.95 CODUS 142 Colebrook Road Sharley Solihull B90 1BX (United Kingdom) tel: +44 121 693 3116 fax: +44 121 693 3116 E-mail: mroughton@fdgroup.co.uk EP 21468 NETPACK Network of Excellence in Microelectronics System Integration Technologies - Packaging Summary Packaging and interconnection technology is essential for the realisation and manufacturing of all electronic equipment. It also determines to a large degree the overall system engineering approach which is adopted, including design, assembly and test. During the last few years packaging and interconnection has received growing attention from the industry as a way to achieve system integration: The spectrum of existing technological approaches is becoming broader with the incorporation of emerging types of construction and innovative combinations of materials and processes. To make the best use of the capabilities of assembly technologies, system manufacturers need to have access to - and master - a variety of technological routes. In all cases a thorough understanding of the available techniques, their strengths and weaknesses, their impact on performance and reliability, and very particularly the associated cost aspects are essential from the component, subsystem and system producers to succeed in world markets.
· Identify packaging activities in Central and Eastern European countries and potential areas for cooperation. · Presentation and publication of "European Packaging" journal. · Contribute to the conception of European R&D programmes. · Develop technology roadmaps for different packaging applications. · Establish a packaging communication electronic network. · Present status and future evolution of CSP (Chip Scale Packages). · Establish links with Known-Good-Die action and Europractice-MCM. · Organise NETPACK sessions in conjunction with major events on Packaging and Interconnection.
The main objective of this Dissemination Activity is to disseminate the results of ESD-projects, both of Application Experiments and of Demonstration Projects to the electronic system design community in Europe. For this purpose, there is first a process for collecting information on applied methods and tools, approaches used and experiences gained. This may include novel design methods and tools from CAD vendors and stable prototypes from European research activities. This information is then made available by various means to the participants of ESD projects and later also to a wider electronic community with emphasis on SMEs in Europe. Objectives · To promote and encourage the widespread use of advanced ESD technology in Europe with emphasis on users from SMEs. · To build up a broad level of know-how on ESD methods and tools including their merits and shortcomings with respect to a wide area of practical applications. · Help to improve the quality and efficiency of system design products on a larger scale. · Contribute to shorten the learning curve for new system designers resulting in shorter time-to-market products at a higher level of product quality. · Bring together potential partners for technological cooperations across Europe to achieve improved competitiveness of European industries on international markets. Participants German National Research Centre for Information Technology, GMD/SET, (D); Politecnico di Torino, (I); Univ. Joseph Fourier, (F) Contact Point Duration Karl H. Glaesser 24 months from 01.12.95 GMD/SET P.O. Box 1240 D 53757 Sankt Augustin (Germany) tel: +49 2241 142048 fax: +49 2241 142342 Email: glaesser@gmd.de Internet: http://set.gmd.de/SYSLINK EP 21972 EARNEST ECSI Awareness Reflection Network for Electronic System Design Standards Summary The awareness of existing Best Practice and modern design and development methods is crucial for European industry products competitiveness in terms of time-to-market, quality and reliability. EARNEST is a European-wide dissemination activity aimed at the promotion of awareness of existing Best Practice, tools, methods and standards in the domain of electronic system design (ESD). It will provide information, advice and promotion of the collected and processed material in order to ensure that European companies, varying from large multi-nationals to SMEs, have appropriate access to Best Practice experience and standards related information. Objectives Collection of the material to be disseminated in paper and electronic form from ECSI Industrial Members, from other Dissemination Actions, standardisation organisations, user groups and other relevant sources. Classification of the information to match the target audience needs. Dissemination of the material to the targeted audience in a packaged and directed form. Preparation of workshops for European Best Practice projects participants. Preparation of Executive Digests of the material. Provision of a coordinated mechanism to access the documentation. Support of other EC projects, including Application Experiments, Demonstration Projects and other projects supported under the Framework IV Programme, through dissemination activities and consultancy. Participants ECSI (F), TUW (A), UM (GB), UPM (E), KTH (S), EPFL (CH). Contact Point Duration European CAD Standardisation Initiative 12 months Parc Equation 2, avenue de Vignate F-38610 Gières (France) tel: +33 76 63 49 34 fax: +33 76 42 87 87 Email: ecsi@grenet.fr, office@ecsi.alpes-net.fr EP 20713 NEXUS Network of Excellence in Multifunctional Microsystems Summary The network of excellence NEXUS provides an industrial and academic forum to accelerate the dissemination of information using microsystem technology (MST) in industry in order to secure the European position during the industrialisation phase of MST. The organisation consists of an industrially led board, an academic working group and four user clubs headed by industrial chairpersons. FhG ISiT provides a general coordination and runs the NEXUS office. Objectives · Provision of an industrial forum and appropriate infrastructure to facilitate the interdisciplinary cooperation that is needed to design and manufacture products using microsystem technology. · Systematic identification of specific application opportunities by organisation of industrially driven user clubs in all important fields of applications. · Elaboration of long-term perspectives for R&D and providing inputs to the growing number of private and public initiatives. · Establishment of a common European MST representation at European and international forums, and in international events including the initial world-wide discussions on standardisation. · Establishment of a world wide web based MST information network and monitoring of progress in MST on a world-wide scale. · Organisation of publicity and awareness activities in the field of MST. · Organisation of task forces to address specific MST related issues such as, production equipment for MST. Executive Board members and coordinator only: FhG ISiT (D), Sextant Avionique (F), GEC-Marconi (UK), SensoNor (N), Schlumberger-GEM (F), CRL (UK), Daimler-Benz (D), MicroParts (D). Contact Point Duration Dr. Hans-Christian Petzold 15 months from 01.10.95 FhG ISiT Dillenburger Strasse 53 D 14199 Berlin (Germany) tel: + 49 30 82 998 110 fax: +49 30 82 998 199 Yüklə 1,25 Mb. Dostları ilə paylaş:
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