Ep optima synopsis

Participants

Codus (UK), IMEC (b), Philips (CH), Eltek (UK), Rood Technology (NL), GPS (UK), Matra MHS (F), Temic (D), Alcatel-Mietec (B), Siemens (D)
Contact Point Duration

Mike G. Roughton 30 months from 01.11.95

CODUS

142 Colebrook Road

Sharley Solihull

B90 1BX (United Kingdom)
tel: [phone]

fax: [phone]

E-mail: [e-mail]

EP 23218 ABEL

Automated Back-End European Line
Summary

The current state of the art for silicon packaging is to use automatic stand alone machines for each process step. Driven by a better customer service and manufacturing optimisation, a partial integration of a few processes steps is proposed by some back-end equipment and manufacturers. The goal of ABEL is to achieve a complete automated and CAM controlled back-end line (Die and wire bounders, moulding, dambar cutting and laser marking systems, trim and form machine).

Objectives

• 
  To develop the hardware interfaces and software tools which are needed for integration of a fully automatic back-end line, with a particular emphasis on scheduling, flexibility, traceability, SPC, equipment data logging.
  
• 
  To improve the stand alone equipment reliability (up-time) and calibration tools to the level necessary for a successful line integration.
  
• 
  The processes and materials will be developed to meet the short cycle time of the automated line concept.
  
• 
  To develop tools for process control and auto-correction of critical process parameters.
  

Partners

SGS-Thomson SA (F); SGS-Thomson Srl (I); FICO (NL); ESEC SA (CH); SGS-Thomson Ltd (M)
Contact point Duration

Juan Exposito 36 months from 01/11/96

SGS-THOMSON Microelectronics

38019 Grenoble Cedex (France)
tel: [phone]

fax: [phone]

E-mail: [e-mail]





EP 23261 FLINT

Fine Line Interconnect
Summary

The principle objective of the project is to provide advanced laminate substrate technologies for use in the rapidly emerging market for high-density electronic products such as lap-top computers, portable phones, as well as MCM-L (multi-chip-module-laminate) for desktop products. These new substrate technologies utilise new hole formation approaches such as laser drilling, plasma etching, photo formation, and are vital for a cost-effective and high-density solution necessary for further miniaturisation.

By designing, building and testing functional demonstrators, enhanced packaging technologies for manufacture and assembly are to be developed in the field of advanced printed circuit boards and laminated organic MCMs. The demonstrators are designed to serve as electronic building blocks in real products in communications applications. Furthermore, the technology is considered to be suitable for the design of subsystems in the market segments of consumer products, automotive and other industrial applications.

Objectives

· Advanced PCB and MCM-L technology comprising circuitry with fine tracks and gaps in high volume manufacturing at competitive prices;

· Reduced track widths down to 50µm;

· Micro-vias utilising laser, plasma and photolithography with diameters down to 50µm;

· Assembly techniques on PCB and MCM-L carriers for flip-chip, wirebond and mixed SMT;

· Integrated resistors and capacitors;

· cost modelling and technology roadmaps based on assessing application requirements for future products;

· Functional demonstrators based on applications for communications.

Participants

STP (D), Solectron (F), GEC-Marconi (UK), Intracom (Gr), NMRC (Irl), BPA(UK)
Contact Point Duration

Dr. Peter Fink, 36 months from 01.10.96

STP Elektronische Systeme GmbH

P.O.Box 560, D-71047 Sindelfingen, (Germany)
Tel: [phone]

Fax: [phone]

E-mail: [e-mail]
EP 23769 CUMULUS

Development of a generic, low cost MCM-L technology for use in portable consumer, automotive and industrial applications

Summary

The Multi-Chip Module (MCM) technology will be made more attractive for use in communications, automotive, industrial and consumer electronics applications.

This will be realised by the development of a highly miniaturised and low overall cost MCM technology. It comprises innovative and low cost production processes at all levels- components, first level interconnect, substrates, second level interconnect- of the MCM architecture. The goals can be achieved through:
Objectives

• 
  Components: Usage of flip chip with pitch down to 150 m or with redistributed pitch down to 250 m as well as Chip Scale or Chip Size Packages (CSP), peripheral pitch down to 200 m or grid array pitch down to 300 m.
  

• 
  First level interconnect: Mounting onto filled and tented vias. Reflow soldering for fine pitch flip chip, combined with underfill. Flip chip and SMD on flexible substrates combined using adhesive technology.
  

• 
  Substrates: Fine line multilayer substrates with lines and spacing down to 50 µm, both in rigid and flex form with via in pad technology realised by photo imaging or laser drilling.
  

• 
  Second level interconnect: Interconnect to the outer world, through a moulded injection device ( MID).
  

Participants

Philips CFT (NL); Combitech Electronics (S); IMEC (B); IVF (S); Siemens (D); TU Berlin (D); Cicorel (CH); STP (D); Shellcase (Isr).

Contact Point	Duration
Co van Veen	36 months from 01.01.97
Philips CFT-SAQ p246
P.O. Box 218
5600 MD Eindhoven (The Netherlands)
Tel: [phone]
Fax: [phone]
E-mail: [e-mail]

ESPRIT 23910

INTEGRATION OF MAGNETICS AND PASSIVE COMPONENTS

Summary

The project is oriented towards the development of high power integration, low voltage and low cost miniaturised DC/DC power converter modules for Telecom applications.

The main objective is to achieve an integrated converter by the innovative use of multilayer technology and suitable electrical conversion topology. New multilayer technology permits the integration of most of the passive components, tracks and interconnections, of low voltage (3,3 V output) and low power ( 10 W ) DC/DC converter.
Objectives

• 
  High efficiency (more than 83% ) DC/DC converter modules by using integrated passive components to give both reduced surface area and small volume: 20x20x4mm
  
• 
  To develop cost effective processes and technologies in order to integrate the passive components (Magnetics, capacitors and resistors) used in low power DC/DC converters.
  
• 
  Develop advanced topologies to maximise energy conversion performance in DC/DC converters.
  
• 
  Produce a design and develop the structure for a DC/DC converter module demonstrator of high reliability with improved volumetric efficiency.
  

DC/DC converter module view with Participants__Alcatel_Mietec_(B);'>Participants'>IMPASS technology
Participants

Alcatel (E); AVX (UK); Universidad de Oviedo (E)

Contact Point Duration

Carlos Quiñones	24 months from 01.03.97
Alcatel Alsthom
Corporate Research Center
Ramirez de Prado,5 Madrid 28045-SPAIN
Tel: [phone]
Fax: [phone]
E-mail: [e-mail]

EP 24363 HIPERPRINT

High Performance Printed Boards and Subassemblies for Telelcom and Rf Applications

Hiperprint
Summary

In Hiperprint a cost-effective modular, high volume, high frequency technology for printed subassemblies will be developed. The core of the technology is oriented towards advanced digital circuits operating at frequencies up to 622 Mbits/sec. The technology to be developed uses the latest improvements in cost-effective flip chip, µBGA and multilayer fine line technology. Assembly will cope with silicon ICs, GaAs MMICs and mixed assemblies (cfr. SMT components). The technology will be validated by means of high volume digital telecom circuits and high-end RF demonstrators. The project results will be made available to other users through the exploitation plans of the consortium partners.

Objectives

• 
  advanced high density multilayer board technology: 2 layer fan-out capability > 500 I/O with 0.2 mm array component path, 50 µm line width and spacing including microvias, integrated resistors and capacitors.
  
• 
  reworkable low cost assembly technology for flip chip and µBGA, using high melting metal bumps or elevated solderpads on the board side for flip chip and µBGA.
  
• 
  development of a digital telecom demonstrator for high volume telecom access circuits (frequency range up to 3GHz)
  
• 
  development of a RF analogue demonstrator operating in the frequency range 12,75-14,5 GHz.
  
• 
  further improvement of design tools and characterisation methods for process modelling, electrical modelling, thermomechanical modelling and devolpment of physical models and libraries tools for fine line printed circuit boards.
  

Participants__Siemens_(D)'>Participants

Design to Distribution (UK), Alcatel Bell (B), Solectron (UK), Alcatel Espace (F), Alcatel Mietec (B), Imec (B)
Contact Point Duration

Brian Smith 36 months

D2D

West Avenue, Kidsgrove

Stoke on Trent,

Staffs ST7 1TL 5 (United Kingdom)
tel: [phone]

fax: [phone]

EP 24366 BATEL

Ball grid array technologies for advanced telecom applications
Summary

In the BATEL project plastic ball grid array (BGA) packages, which are currently the best choice with respect to high pincount, high density, high performance and SMT capabilities, will be developed to meet a number of stringent telecom application requirements, such as the need for thinner packages with high pincounts and reduced grid pitches.

Medium ballcount (± 200 balls) thin BGA’s with a grid pitch down to 0.5 mm and a reduced profile down to 1.4 mm total thickness with chip scale potential will be developed. The developed BGA packages will be validated by means of an advanced GSM telecom demonstrator, processed in 0.35 µm CMOS.
Objectives

• 
  To develop a thin chip scale BGA package of medium ball count, with a grid pitch of 0.5 mm and a thickness of 1.4 mm
  
• 
  To fully characterise the developed BGA packages and make them available for reliability assessment, surface mounting on PCB and product validation.
  
• 
  To develop suitable systems for the handling and inspection of thin BGA packages.
  
• 
  To develop specific printed circuit board assembly techniques for the developed high density array packages.
  
• 
  To perform a thorough evaluation of the related plastic packaging enhanced reliability problems through advanced test vehicles and characterisation methods.
  
• 
  To qualify the developed thin chip scale BGA packages by product validation techniques using a selected telecom demonstrator circuit.
  
• 
  To monitor the cost-effectiveness of the developed BGA packages.
  
• 
  To issue guidelines for exploitation of the developed BGA packages in typical telecom system applications.
  

Participants

Alcatel Mietec (B); SGS-Thomson Microelectronics (F); Alcatel Mobile Phones (F); SCI France (F); Alcatel Bell (B); NMRC (IRL); SGS-Thomson Microelectronics (I); Multitest (D); ICOS (B).

Contact Point	Duration
Dr Gust Schols	36 months from 01.01.97
Alcatel Mietec
Westerring 15
B-9700 Oudenaarde (Belgium)
Tel: [phone]
Fax: [phone]
E-mail: [e-mail]

EP 26245 ESCHETA

European Sources of Chip Scale Packages for Harsh Environment, Telecom & Automotive
Summary

The project targets the development, qualification and industrialisation of different European Chip Scale Package (CSP) sources with respect to their applicability in various environmental conditions such as telecom and automotive (Harsh Environment).

Three distinct approaches of chip scale package type constructions based on wafer level, flexible tape and rigid carrier redistribution will be followed, capable to meet ball pitches from 1.0 mm down to 0.5 mm depending on the application’s needs. The developed packages will be characterised by simulation and fully qualified under conditions required for telecom and automotive applications. In addition to single chip package long-term reliability, industrialisation processes such as solder joint reliability, surface mount assembly compatibility, PCB layout & design rules, repair & rework are addressed. In parallel, the developed European CSP approaches will be benchmarked, in the same application contexts, against commercially available CSP packages.

The applicability and industrialisation of the CSPs will be validated by means of two demonstrators covering the automotive volume market for harsh environment and complex telecom systems with high power requirements.

Objectives

• 
  to develop and establish various CSPs which will be provided by European sources.
  
• 
  to qualify the CSPs for usage under telecom and automotive conditions.
  
• 
  to validate the feasibility and manufacturability in a standard SMT process by setting up fully functional demonstrators for automotive and telecom switching (high power) application.
  

Participants

Alcatel SEL (D), Bull (F), Matra BAe (F), Siemens-HL (D), Siemens-AT (F), TU Berlin (D), EM Microelectronic Marin (CH), PacTech (D)
Contact Point Duration

Dr.Thomas Solleder 36 months from 01.02.98

Alcatel SEL AG

Lorenzstr. 10 , D-70435 Stuttgart, Germany

Tel: [phone]

Fax: [phone]

E-mail: [e-mail]

EP 26261 LAP

Low cost Large Area Panel Processing of

MCM-D substrates and packages
Summary

The main LAP objective is the development and demonstration of low cost high-density substrate manufacturing technology for first level die assemblies.

The cost target for high volume production of this high density interconnect substrates is as low as 1 US$/in² and shall be obtained by increasing panel size of today to panel areas up to 24 x 24 in² - the maximum practical panel size of today. While this largest thinkable panel size will probably remain an object of studies and experiments, 8 in , 12 x 12 in², and 16 x 16 in² are candidates for HDI production in the year 2000.

The substrate technologies developed will allow for a wide range of packaging options from inserted substrates into transfer-molded packages to integrated MCM-L/D and MCM-M/D (M=metal) area array packages. The suitability of the LAP technology will be demonstrated with three products from the communication, instrumentation and telecommunication sectors.

Objectives

• 
  High density / low cost substrate technology (capable for interconnecting 1000 I/O /in² by use of standard 1^st level assembly processes) with a production cost target of 1US$ / in².
  
• 
  Development of a high performance MCM-D technology with 50 µm line pitch and 50 µm via/land to be verified by prototyping (cost will definitely be higher than 1US$/in²).
  
• 
  Verification of the technical target by prototyping on a LAP pilot line and verification of the cost target by appropriate cost modelling for a high volume production facility.
  
• 
  Qualification of the LAP technologies for semiconductor assembly into QFP and BGA.
  
• 
  Compatibility of the LAP technologies of the three manufacturers within a specified range of design rules and qualification requirements (to be specified during the project).
  
• 
  Verification of the LAP technologies developed by three product demonstrators.
  

Participants

Siemens (D), CAEN (I), Hirschmann (D), Strand (S), Thomson (F), ETH (CH), IMC (S), NMRC (Irl)

Cooperative link with FLIPAC Consortium

Contact point Duration

Dr. Peter Demmer 30 months from 01.01.98

Siemens AG, ZT ME 6

Otto-Hahn Ring 6,

D-81739 München
Tel: [phone]

Fax: [phone]

E-mail: [e-mail]

EP 26280 FLIPAC

Fine Line Interconnection and Packaging
Summary

As advances in semiconductor technology create larger devices with more contacts, greater functionality, higher speed and greater power dissipation, appropriate packaging is essential for proper application in electronic systems.

The FLIPAC project aims at developing higher density interconnections and packaging solutions in order to build printed circuit boards and MCM-L/D substrates to address the needs of advanced data processing and telecom applications. An increased level of integration will be reached through the assembly of large bare die using flip-chip, TAB, wire bonding and CSP technologies. Potential applications include also robotics and automation, transport (land, sea and air), medical electronics and consumer products.

Within the project, build-up printed circuit boards using enhanced processes and materials, will be developed and compared. Functional MCM-L/D demonstrators for Data Processing and Telecommunication industry solutions will be designed, built and tested. Industrial capability and cost are also addressed.

Objectives

• 
  capability to build advanced organic substrates for the interconnection of large size bare dies (flip-chip, wire-bonding, TAB) and area components (BGA, CSP) ;
  
• 
  enhancement of thermomechanical properties and reliability of MCM-L substrates by the use of new organic core material ;
  
• 
  extension of results to a new cost effective high density printed circuit board technology on large substrate size (large area processing) ;
  
• 
  cost reduction of printed circuit boards by reduction of the number of layers ;
  
• 
  definition of design rules ;
  
• 
  capability to build advanced modules for Data Processing and Telecommunication industries ;
  
• 
  achievement of a cost / performance ratio competing with existing multilayer PCB technologies, as well as with existing MCM-C and MCM-D solutions ;
  

Participants

Bull (F), Bull (I), Cimulec (F), Dicryl (E), IMC (S), IMEC (B), Italtel (I), LinLam (Nl), TU Berlin (D)

Cooperative link with LAP consortium

Contact Point Duration

Dr Karel Kurzweil, 30 months from 01.01.98

Bull SA

Rue Jean Jaurès 68

78340 Les Clayes Sous Bois (France)
Tel: [phone]

Fax: [phone]

E-mail: [e-mail]

EP 21315 GAMMA

Gallium Arsenide Materials for Microwave Applications
Summary

GaAs technology for both discrete and IC components has proved to be indispensable for advanced telecommunication and automotive systems. The use of GaAs clearly starts where the silicon ends i.e. in meeting system requirements such as the RF front-end of mobile communication equipment, broadband radio links and anti-collision systems.

The main interest of this project is to develop and qualify semi-insulating bulk GaAs and epitaxial material for three major microwave applications: MESFETs, pseudomorphic HEMTs and GaInP-HBTs; and to establish competitive European production facilities in those domains.
Objectives

• 
  Establishing a reliable European source for 4" semi-insulating GaAs substrate fabrication, optimised for ion implantation applications. Comparison of 3" and 4" state-of-the-art world market material.
  
• 
  Epi-ready wafers directly usable for an MBE process. Attention will be paid to the requirements on geometry and surface conditions.
  
• 
  Production and qualification of high performance 4" MBE-grown P-HEMT epiwafers. Tests will be performed by a device supplier (SIE) to evaluate the material quality.
  
• 
  Comparison of the P-HEMT structures grown by MOVPE and MBE processes. In addition, application and quality as factors in production will be addressed.
  
• 
  Establishing a European commercial source of GaInP/GaAs HBT epitaxial wafers. Evaluation and characterisation of materials developed by EPI and IAF by the industrial users in their standard production lines.