Hybrid adders are a combination of two or more of classic addition circuits to provide high efficiency in terms of performance criteria such as high speed, small chip area and low power consumption. In this work, a new systematic design method for a high performance hybrid adder has been proposed that is used in implementation of arithmetic circuits. Here the main objective is to select the sub-adder types constituting a high performance hybrid adder and to allocate the optimal values of these sub-adders bit widths.
The results demonstrated that Linear Programming based proposed method is succeeded in finding the optimal topology of a high performance hybrid adder. Moreover, the proposed method has provided better results in terms of delay / area and delay / power optimization in comparison to the classical adder design methods.
