International organisation for standardisation organisation internationale de normalisation

5.8.3Combined approaches

5.8.3.1.1.1.1.1.1JCTVC-H0277 Non-CE8: Additional simulation results of SAO and ALF [T.-D. Chuang, Y.-W. Chen, J.-L. Lin, Y.-W. Huang, S. Lei (MediaTek)]

5.9NSQT/SDIP harmonization

Note AHG report JCTVC-H0016.

5.9.1.1.1.1.1.1.1JCTVC-H0347 AHG16: SDIP unified with NSQT [X. Cao, Y. He (Tsinghua), X. Peng (USTC), C. Lai, X.Zheng, L. Liu, J. Zheng (HiSilicon), J. Xu (Microsoft), H. Yang, J. Song, H. Yu (Huawei), J. Lim, B. Jeon (LGE), J. Sole, L.Guo, X. Wang, M. Karczewicz (Qualcomm), J. Xu, E. Maani, A. Tabatabai (Sony), X. Zhang, S. Liu, S. Lei (MediaTek)]

This contribution reported the results of a unification of SDIP and NSQT. SDIP with 2NxN/Nx2N and 2NxhN/hNx2N PU were tested with the same non square TUs as with NSQT. Results with or without 8x2/2x8 TUs were also reported. For the all-intra HE case, when 2x8/8x2 TU are used, 1.8% and 1.7% gain can be achieved with 128% and 130% encoding time increases for SDIP with 2NxN/Nx2N PU and SDIP with 2NxhN/hNx2N PUs, respectively. Without 2x8/8x2 TUs, for SDIP with 2NxN/Nx2N PUs and SDIP with 2NxhN/hNx2N PUs, the gain is 1.0% and 1.0%, with 117% and 119% encoding time increases. No obvious decoding time increase was reportedly observed. Note: "hN"="Half N".

Some reservations were expressed against 2x8 and 8x2 modes. These are also not in harmony with the current non-square inter coding.

It was asked how de-blocking is done. This was said to be at 8x8 boundaries, as in NSQT.

For intra-only coding without 8x2, no remarkable difference between Nx2N and hNx2N was reported.

Two WD texts were included – one for Nx2N, one for hNx2N. Neither of them includes 2x8/8x2.

For RA coding, the BD BR gain is 0.9% with the 2x8/8x2 modes, and 0.4% without (Nx2N/2NxN), and a little bit more for hNx2N.

More information was requested to understand what are the detailed changes.

The encoder implementation uses an early skip decision for non-square blocks.

A short review of the WD text version for Nx2N was done which unveiled that various changes are necessary to the decoding process of intra (PU, MPM, mode derivation, transform, deblocking filter).

A new version was also shown which had not yet been uploaded.

Concerns were expressed about the maturity of the text, the amount of changes and implications on decoders, and also about the complexity of encoders. No action was taken.

5.9.1.1.1.1.1.1.2JCTVC-H0106 AHG16: Crosscheck of SDIP and NSQT harmonization (JCTVC-H0347) [T. Yamamoto (Sharp)] [late]

5.9.1.1.1.1.1.1.3JCTVC-H0300 AHG16: Crosscheck of SDIP and NSQT unification (JCTVC-H0347) [Y.J. Chiu, L. Xu, W. Zhang, Y. Han (Intel)]
5.9.1.1.1.1.1.1.4JCTVC-H0455 AHG16: Harmonization of 2NxN/Nx2N Intra PU with SDIP and NSQT [X. Zhang, S. Liu, C.-W. Hsu, T.-D. Chuang, S. Lei (MediaTek)]

This contribution proposed a set of methods for harmonization of 2NxN/Nx2N PUs with SDIP and NSQT. The coding efficiency and run-time of the proposed methods built on top of AHG16 software were reported. Experimental results reportedly average 1.8% BD bit rate reduction for All Intra HE with encoding runtime increased by 32% and decoding runtime increased by 3% with 8x2/2x8 transforms enabled. Experimental results reportedly average 1.4% BD bit rate reduction for All Intra HE with encoding runtime increased by 31% and decoding runtime increased by 2% when 8x2/2x8 transform was disabled. With further encoder complexity reduction, experimental results reportedly average 1.2% BD bit rate reduction for All Intra HE with encoding runtime increased by 23% and decoding runtime increased by 2%. By applying the proposed PU type signalling method on 2Nx0.5N/0.5Nx2N intra prediction units, experimental results reportedly average 0.0% BD bit rate difference for All Intra HE with negligible encoding and decoding runtime changes compared to AHG16 software. Two context models were removed.

No WD text was available, but it was said that it would be identical to the text of JCTVC-H347 (the variation with Nx2N).

5.9.1.1.1.1.1.1.5JCTVC-H0302 AHG16: Crosscheck of MediaTek harmonization of 2NxN/Nx2N Intra PU with SDIP and NSQT (JCTVC-H0455) [Y. J. Chiu, L. Xu, W. Zhang, Y. Han (Intel)] [late]

5.9.1.1.1.1.1.1.6JCTVC-H0558 Cross-Check of AhG16: SDIP [Ankur Saxena, F. Fernandes (Samsung)] [late]
5.9.1.1.1.1.1.1.7JCTVC-H0492 Clean-up of NSQT implementation [Y. Yuan (Tsinghua), X. Zheng (HiSilicon), H. Yu (Huawei), Y. He (Tsinghua)]

This contribution provided a proposal of NSQT implementation. In particular, the proposed solution reportedly merged the derivation of square and non-square TU address derivation, removed redundant codes related to non-square transform block operation, and unified the software design of square and non-square transformation process. After the clean-up, nearly 1000 lines of code could reportedly be removed relative to HM5.0, and the coding styles of square quadtree and non-square quadtree could be made more consistent.

This removed approximagely 1000 lines of code by unifying square and non-square transform usage. A slight deviation of results was reported, due to a bug fix in BS calculation. This was confirmed by a cross-checker.

Decision (SW): Adopt (software only).

5.9.1.1.1.1.1.1.8JCTVC-H0605 Cross-check of JCTVC-H0492 on Clean-up of NSQT implementation [E. François (Canon)] [late]