International organisation for standardisation

Joint meeting with 3DG subgroup

Discussion and conclusions are reported in the report of the 3DG subgroup of WG11.

Review of Input contributions

Document No.	Title	Authors
	Notes & Disposition
M20024	FPGA Dynamic reconfiguration using the RVC technology: Inverse Quantification case study	Manel Hentati, Mohamed Abid, Yassine Aoudni, Jean François Nezan
	The contribution presents an investigation on how the RVC specification can support the dynamic reconfiguration of an FPGA implementation. The case study considers the reconfiguration of a quantization matrix. This implies two modifications: one in the parser to recover the quantization matrix and another in the quantizer. Two options are possible in RVC. In the first case the FU in the VTL supports the change of the matrix, so no dynamic reconfiguration is necessary. In the second case two versions exist in the VTL (with and without change of matrix) and the implementation can be based on one version or on the other depending whether the implementation can support dynamic reconfiguration. Recommendation: Continue the experimentation before proposing a change in the VTL to demonstrate partial reconfiguration capabilities.
M20074	Report on Performance of Generated Code (C, LLVM, and VHDL) from RVC Descriptions		Damien de Saint Jorre, Jérôme Gorin, Jean-François Nezan, Mickaël Raulet, Nicolas Siret, Matthieu Wipliez, Hervé Yviquel
	This contribution presents a report of the performance of code generated by a RVC specification for both SW and HW. It reportedly shows that high performance can be reached directly by the RVC specification and the code is portable and scales on platforms with more processors. Recommendation: The development of supporting tools has been shown to be beneficial for RVC development, and further work on this recommended.
M20075