International organisation for standardisation

5.9.3Discussion and Conclusions

5.10CE10: Core transform design

5.10.1Summary

5.10.1.1.1.1.1.1.1JCTVC-F030 CE10: Summary report of Core Experiment on core transform design [P. Topiwala, M. Budagavi, I. Kim, R. Joshi (CE coordinators)] [upload 07-12]

Four core transform proposals were considered:

1. 
   Cisco/TI (HM3.0, JCTVC-F446),
   
2. 
   Samsung/FastVDO (JCTVC-F251),
   
3. 
   FastVDO/Samsung (JCTVC-F363) different from JCTVC-F251 in 8 and 16 point transform,
   
4. 
   Qualcomm (JCTVC-F352).
   

The summary report does not use a table that differentiates between 16 bit and 32 bit multiplies.

The first three proposals re-use existing quantization; the fourth proposal needs a quant. matrix.

Proposals 1, 2 and 4 have an embedded design, i.e. the smaller size transforms are included as building blocks of the next-larger size. 3 uses a different design (lifting) for 16 block sizes.

A summary of the previous BoG meeting produced by P.T. had previously been sent to the reflector and was also presented in this context. It was disputed whether this summary fully reflected the real opinions of individuals participating in the breakout.

Transforms cannot be judged in terms of RD performance as they are more or less equal (agreed). Data available for understanding implementation complexity:

JCTVC-F251 contains an analysis about itself, JCTVC-F352 and JCTVC-F446 (for hardware and software)

JCTVC-F446 contains analysis about itself for hardware

JCTVC-F447 contains analysis about JCTVC-F446 for software

JCTVC-F710 contains analysis about JCTVC-F251 and JCTVC-F446 for SIMD

As agreed on reflector, analysis was mainly done for the worst case of 32-point transform. This may be OK for the embedded design approaches. For JCTVC-F363, hardware implementation analysis data for the 16-point (lifting) transform would be missing.