Joint Collaborative Team on Video Coding (jct-vc)

3Project development, status, and guidance

3.1Conformance test set development

JCTVC-N0284 Editor's proposed draft text of HEVC conformance testing [T. Suzuki, G. Sullivan, W. Wan] [late]

Further improvement was encouraged.

3.2Version 1 bug reports and cleanup

JCTVC-N0041 Editors' proposed corrections to HEVC version 1 [B. Bross, G. J. Sullivan, Y.-K. Wang]

(Discussed in Track A Tue. 30th (GJS).)

These corrections seemed uncontroversial.

JCTVC-N0094 HEVC version 1 (corrigendum): Derivation of CPB removal time [A. K. Ramasubramonian, Y.-K. Wang (Qualcomm)]

Discussed Thu 1st (GJS):

This document reports that the derivation of nominal CPB removal times of access units in the specification of HEVC version 1 has a bug, more specifically related to the derivation of the variable AuCpbRemovalDelayVal, and proposes a method to fix the issue.

The problem is about how we specified the intended modulo operation of the CPB removal delay.

Decision (BF): Add this to our defect report output document.

JCTVC-N0346 Proposed editorial changes for maximum number of slices and tiles per picture limit [M. Zhou, B. Heng, W. Wan (Broadcom)] [late]

Discussed Thu 1st (GJS):

It is asserted that, based on the calculations specified in the current HEVC version 1 text, the maximum number of slices per picture could be 0 for high levels with small enough pictures. A similar issue is reported in the maximum number of tiles per picture limit.

The issue seems to be an obvious oversight.

Discussed Thu 1st (GJS): Decision (BF): Ensure that at least one slice (and tile) is allowed.
JCTVC-N0378 Clarifications on HEVC NALU order [Jean Le Feuvre (Telecom ParisTech), Cyril Concolato (Telecom ParisTech), Mickael Raulet (IETR/INSA Rennes)] [late]

(Reviewed in Track A Tue. 30th (GJS).)

Previously registered as N0324 (also late).

Contains two elements:

• 
  Regarding first_slice_segment_in_pic_flag, the contribution reported that there is an issue with picture boundary detection – esp. for consecutive IDR pictures. The flag can be lost. Also, the end of one picture may not be detected until receiving the first slice of the next picture. Historically, idr_pic_id was in drafts of HEVC but was removed prior to finalization. It was noted that we don't really expect consecutive IDR pictures to be used commonly and don't encourage them to be used – since CRA pictures are expected to be more appropriate for all-intra use. Also we have a temporal sub-layer zero SEI message that can be helpful if used. Many systems have provisions to assist with this topic (e.g., RTP timestamps, PTSs, AU framing in ISOBMFF, RTP marker bits, MPEG-2 TS PES). It was suggested to add some informative note(s) to discuss the issue and discourage consecutive IDR usage. Decision: Agreed.
  
• 
  Regarding parallel processing, the contribution noted that it is possible to decode tiles and slices in parallel, but we require slices (and tiles) to be in a specific order. It was remarked that this is an old and well-known issue, and the current spec content was carefully negotiated intentionally. Supporting arbitrary order in a decoder is non-trivial. Removing this constraint would require defining a new profile, which is unlikely to be justified. Unless it is known that a decoder can handle out-of-order NALUs, it may be necessary for encoders or receivers to buffer and order NALUs in the specified conforming order.
  

3.3Implementation demonstrations

JCTVC-N0313 4EVER HEVC demonstrations during Roland Garros tournament [S. Kervadec (Orange Labs), M. Raulet (INSA), J. Le Feuvre (Telecom Paris Tech), J. Vieron (Ateme), M. Clare (Orange Labs)] [late]

This contribution described an end-to-end live HD HEVC-based delivery chain that was demonstrated by the 4EVER project during the French Open Tennis Tournament Roland-Garros.

Several MPEG/ITU technologies were reportedly showcased during these demonstrations. Demonstrations were shown during the second week of the tournament, from June 1st, to June 9th.

Three HEVC-based HD End-to-End Live delivery chains were demonstrated: IPTV chain, based on HEVC/MPEG-4 AAC/MPEG-2 TS, delivered using UDP multicast transport over an Orange IPTV managed network; an Internet chain, based on HEVC/MPEG-4 AAC/ISOBMFF/MPEG DASH, delivered using HTTP over best-effort Internet network, through two different (nominal/backup) HTTP servers; a DVB-T2 chain, based on HEVC/MPEG-4 AAC/MPEG-2 TS, delivered over DVB-T2 modulation.

These demonstrations were reportedly operated in the same conditions as any commercial audiovisual service, the IPTV and Internet Live feeds being broadcasted at the same time they were produced on the courts, and being accessible through any Orange access (although requiring a dedicated HEVC decoder).

No action was requested; the presenter not present Thu pm.

JCTVC-N0276 A hardware oriented implementation of HEVC encoding [Ryoji Hashimoto, Seiji Mochizuki, Kenichi Iwata (Renesas)]

Reviewed Thu 1 a.m. (GJS).

This contribution presents a hardware oriented implementation of HEVC encoding, which makes control logic in encoder easier. A hardware encoder can extend input images to multiple of CTB size by utilizing the conformance window syntax to simplify control logic. However, extension of images requests more bits to encode, especially with large CTB size. To minimize overhead of bits in extended area, truncation of coefficients in quantization and optimization of TU partitioning and process are adopted. As a result, adopted methods in developed hardware can reportedly save 6.3% the BD rate in maximum.
JCTVC-N0043 On software complexity: real time and parallel SHVC video decoder [W. Hamidouche, M. Raulet, O. Déforges (IETR/INSA)]

(Contributor indicated that detailed presentation was not necessary – please see contribution submission.)

This contribution describes an open source SHVC software decoder implementing the reference index based SHVC design. The wavefront parallel processing approach is used to perform the video decoding of both the base layer and the enhancement one in parallel.

Experimental results carried out on a laptop fitted with a core Intel i7 processor reportedly show that the demonstrated software decoder achieves the decoding of 1280×720 base layer and 1920×1080 enhancement layer video sequences at 25 fps when using four concurrent threads.