MicroWind manual

3. Design of a CMOS Inverter

This chapter is dedicated to the layout design of a simple CMOS inverter. You will learn how to draw manually all the elements of the cell (i.e. boxes, layers, text, and properties). You will use the design tools quite intensively.

The CMOS Inverter
The CMOS inverter includes 2 transistors. One is a n-channel transistor, the other a p-channel transistor. The device symbols are reported below. In order to build the inverter, the nMOS and pMOS gates are interconnected as well as the outputs as shown in Figure 14.

Fig. 14. The schematic diagram of the CMOS inverter with one nMOS at the bottom and one pMOS at the top.
Manual Design

Using the following procedure, you can create a manual design of the inverter. The default icon is the drawing icon shown above. It allows box editing. The display window is empty. The palette is located in the lower right corner of the screen. A red color indicates the current layer. Initially the selected layer in the palette is polysilicon. The two first steps are illustrated in Figure 15.

ΠFix the first corner of the box with the mouse.

 While keeping the mouse button pressed, move the mouse.

to the opposite corner of the box.

Ž Release the button. This creates a box in polysilicon layer as shown in Figure 24.

The box width should not be lower than 2 l, which is the minimum width of the

polysilicon box.

Fig. 15. Creating a polysilicon box.
Now, draw two more boxes as in Figure 16. Try to keep close to the shape and size of the example.



Fig. 16. Creating three polysilicon boxes.
Change the current layer into N+ diffusion by a click in the palette on the Diffusion N+ button. Be sure that the red layer is now the N+ Diffusion. Draw a n-diffusion box at the bottom of the drawing as in Figure 17. N-diffusion boxes are represented in green. The intersection between the N+ diffusion and the polysilicon creates the channel of the MOS device.


Fig. 17. Creating the N-channel and P-Channel devices.

Change the current layer into P+ diffusion by a click in the palette on the button P+ Diffusion. Draw a p-diffusion box at the top of the drawing as in Figure 29. N-diffusion boxes are represented in green. The intersection between the P+ diffusion and the polysilicon creates the channel of the pMOS device.

Change the current layer into N Well by a click on the corresponding button in the palette. Draw a well all around the p+ diffusion, as in Figure 18. Use keyboard arrows (up key) to view the upper part of the layout.


Fig. 18. Creating the well for the P-Channel Device.
Process Simulation

Click on this icon to access « process simulation ». The cross-section is given by a click on the mouse at the first point and the release of the mouse at the second point. In the example below (Figure 19), the cross-section of the n-channel MOS device appears on the left, and the cross-section of the p-channel MOS device on the right.

Fig. 19. The cross-section of the nMOS and pMOS devices.


Contacts and Metal Interconnects

The diffusion areas must be joined using a metal layer. The metal layer is isolated from the diffusions by a thick silicon dioxide SiO2 layer. The contact layer is used to drill a hole in the oxide in order to join the metal and the diffusions. You could draw the contact box manually by selecting the layer « Contact » and drawing a 2 x 2 l box.

A fast solution is to use the predefined macros at the top of the palette. Various contacts built according to design rules are proposed.


Fig. 20. The contact macros.
Choose the diffn/metal contact icon in the palette. The contact outline will appear. Fix the contact inside the n+ diffusion area. Click again on the diffn/metal contact and place it at the upper corner of the n-well box. This contact is used to polarize the well at VDD. The diffusion N+ in the nwell makes an ohmic contact and prepares for the VDD polarization using metal layers. Finally, click on the diffp/metal icon and fix the contact inside the p+ diffusion area.
Select the « metal » layer in the palette. Draw a metal bridge between the n+ and p+ contacts. The CMOS inverter layout is almost completed (Figure 21). The remaining task is to define where the supply, the ground, the input and the output are.



Fig. 21. The metal bridge and the inverter are completed.

Add Properties for Simulation
Properties must be added to the layout to fix the ground, the supply, the input and the outputs. The summary of available properties is reported below.

For the inverter example, we must assign the upper p-diffusion to a VDD power supply, and the lower n-diffusion box to a VSS ground voltage. We also need to specify a clock as the input for the IN node and have a look at the output OUT.

ΠStuck at Vdd: Click on the Vdd icon and click on the upper p-diffusion box.

The Vdd property is sent to the node.
 Also click in the N-Well region inside which the pMOS is located. The NWell

must always be at VDD voltage to keep the pMOS junctions inverted.

 Hold at Vss: Click on the Vss icon, click on the lower n-diffusion box.

The Vss property is sent to the node.

 Apply a clock to node IN: Click on the Clock icon and on the polysilicon gate.

The Clock menu appears (See below). Click on OK. A default clock with 3 ns

period is generated. The Clock property is sent to the node and appears at

the right hand side of the desired location with the name « clock1 ».

Fig. 22. The clock menu.

 Watch the output: Click on the Visible icon and then, on the metal bridge.

The window below appears. Click OK. The Visible property is sent to the node.

The associated text « s1 » is in italic. The chronogram of this node will appear

in the next simulation.


Analog Simulation

IMPORTANT : Always save BEFORE simulation ! Click on File in the main menu. Move the cursor to Save as ... and click on it. A new window appears, into which you are to enter the design name. Type, for example, MYINV. Use the keyboard for this and press ¿. Then click on OK. After a confirmation question, the design is saved under that filename.

Click on Simulate in the main menu. The timing diagrams of the inverter appear, as shown in Figure 23. Click on More in order to perform more simulations. Click on Stop to return to the editor. The gate delay is computed at VDD/2, that is 2.5 V, between the signal selected in the Start Node list and the signal selected with the Stop Node list.

Fig. 23. Analog simulation of the CMOS inverter. The output has the opposite value of the clock input.
¨ Click on Voltage & Currents to see both currents and voltages (Figure 24). The current peaks can be seen in the upper window. All voltages are reported in the lower window. The current scale can be adjusted using a predefined list of values. Some current is consumed at VDD supply, mainly when the output of the inverter rises to VDD. Some current is consumed at VSS, mainly when the output goes down to zero.

¨ Click on Voltage vs. Voltage to see the DC transfer characteristics of the inverter (Figure 24-bottom). The commutation point of the inverter Vc is the input voltage for which the output is close to VDD/2. In the case of Figure 24, Vc is around 1.8 V. Click on Back to Editor to return to the editor.

Fig. 24. Current consumption of the CMOS inverter (top) and DC characteristics of the CMOS inverter(bottom).

Is your layout correct ?

Click on the above icon to answer the question. The Design Rule Checker (DRC) scans the design and verifies a set of design rules. The errors are highlighted in the display window, with an appropriate message giving the nature of the error. Details about the position and type of error(s) appear on the screen.
Only an error-free layout can be sent to fabrication. See Chapter 8 for more details about the design rules and some graphical examples which will help you to understand the origin of the error.
Parametric Analysis of the Inverter
Click on Analysis -> Parametric Analysis. Click on the output node of the inverter in the layout. The window below appears. The parametric analyzer allows you to investigate easily the influence of various parameters on the inverter delay.

Fig. 25. The parametric analyzer

Œ Select the « Delay » in the « Measurement » menu.

 Select « power-supply » in the « Parameter » choice.
 Click on « Start Analysis ». An iterative procedure conducts simulations and extracts the delay from the simulation for each value of VDD power supply as defined in the « Range » menu. The result in Fig. 25 shows that the gate delay decreases rapidly with the power supply.


Fig. 26. Investigation of the VDD supply effect on the power consumption (top), and the effect of the output capacitance load on the delay (bottom).

Other possible investigations concern the frequency and dissipation. The temperature, the node capacitance and the voltage supply are parameters worth of interest are. Fig 26 gives an account of the increase of the power consumption with the VDD supply. Fig 26 also points out (bottom) the delay increase with the output capacitance load.

In order to obtain this curve, you should select the « Node Capacitance » in the parameter list first, and then modify the items « From », « To » and « Step » according to Fig. 26. Once those modifications have been made, you can start the analysis. As expected, the gate delay increases rapidly along with the output capacitance.

Save & Quit

Click on F2 or File -> Save. The design is saved under the current name. The MSK appendix is automatically added to the user’s filename. To leave MICROWIND, click on File->Leave Microwind in the main menu.

4. Basic Gates

The Nand Gate
The truth-table and the schematic diagram of the CMOS NAND gate with 2 inputs are shown in Figure 26. The NAND gate consists of two nMOS in series connected to two pMOS in parallel.

NAND 2 inputs

A B OUT

0 0 1

0 1 1

1 0 1

1 1 0

Fig. 26. The truth table and schematic diagram of the CMOS NAND gate design.

Compiling the Nand Gate
You may load the NAND gate design using the command File -> Read->NAND.MSK. You may also draw the NAND gate manually for the Inverter gate.
An alternative solution is to use the logic editor to generate the verilog description of the NAND gate, and to compile this verilog description into layout. In this case, complete the following procedure:
ΠAdd the NAND symbol, two buttons and one lamp in the logic editor DSCH. Add interconnects and verify the logic behavior of the cell.

 In DSCH, Click on « File -> Create Verilog File », and click on « Save ». The Verilog text is « example.txt ».

Ž In Microwind, Click on Compile->Compile Verilog File. Select « example.txt » in the appropriate directory. The result is reported in Figure 27.



Fig. 27. A NAND cell created by the CMOS compiler.

Simulation of the NAND Gate
The compiler has already fixed the position of VDD power supply and the ground VSS. The texts A, B, and S have already been fixed to the layout.

ΠClick on the Clock icon and click inside the polysilicon box of the gate A.

The clock window appears.

 Click on OK to assign the default clock parameters to A.

Ž Now, click inside the polysilicon box of the gate B. A new clock window appears.

 Click on OK to assign the new clock parameters to B.

Notice that the clock period has been automatically multiplied by two

in order to scan all logic input combinations.

 Click on the Visible icon and on the output node S.
‘ Click on Simulate. The timing diagrams appear as shown in Figure 28.

The rise time is faster because of the pMOS devices in parallel.

Fig. 28. Simulation of the NAND gate.

The 3-Input OR Gate
The truth-table and the schematic diagram of the three-input OR gate are shown in Figure 29. You may use the DSCH logic editor again to design a schematic diagram of the OR gate, generate a Verilog description, and compile the text file in Microwind. As can be seen in the schematic diagram and in the compiled results, the gate is the sum of a NOR3 gate and an inverter. In CMOS, the Negative gates (NAND, NOR, INV) are faster and simpler than the non-negative gates (AND, OR, Buffer).

Once the cell has been compiled, add one clock to each input (A, B and C). Add the visible property to the output out. Then click on Simulate.

OR 3 Inputs

A B C Or3

0 0 0 0

0 0 1 1

0 1 0 1

0 1 1 1

1 0 0 1

1 0 1 1

1 1 0 1

1 1 1 1


Fig. 29. The truth table, design and schematic diagram of the NOR3 gate (NOR3.MSK).


Fig. 30. Simulation of the OR gate with 3 inputs (OR3.MSK).
The XOR Gate
The truth-table and the schematic diagram of the CMOS XOR gate are shown in Figure 46. No simple implementation is possible, even if many different solutions can be given. The proposed solution consists of a transmission-gate implementation of the operator.
XOR 2 inputs

A B OUT

0 0 0

0 1 1

1 0 1

1 1 0

Fig. 31. The truth table and schematic diagram of the XOR gate.
The truth table of the XOR can be read as follow: IF B=0, OUT=A, IF B=1, OUT = Inv(A). The principle of the circuit presented in Figure 31 is to enable the A signal to flow to node N1 if B=1 and to enable the Inv(A) signal to flow to node N1 if B=0. The node OUT inverts N1, so that we can find the XOR operator. Notice that the nMOS and pMOS devices situated in the middle of the gate serve as pass transistors.
The file is called XOR.MSK and is ready for simulation. Click on Simulate in the main menu. Don’t forget to check the chronogram values.
You may also use DSCH to create the cell, generate the Verilog description and compile the resulting text. In Microwind, the Verilog compiler is able to construct the XOR cell as reported in Figure 32.


Fig. 32. The layout design of the XOR gate (XOR.MSK).

SIMULATION. Add clock properties to the inputs A and B, a visible property to the output and verify the truth-table of the XOR gate (Figure 32). You may also add a visible property to the « nxor » intermediate node which serves as an input of the second inverter. See how the signal is altered by Vtn (when the nMOS is ON) and Vtp (when the pMOS is ON). Fortunately, the inverter regenerates the signal.

Fig. 33. Simulation of the XOR gate (XOR.MSK).

Complex Gates

The one-line complex gate compiler is able to generate the CMOS layout corresponding to any description based on the operators AND and OR, also called complex gates. In the equation, the first parameter is the output name. In the present case that name is s. The sign '=' is obligatory. The '/' sign corresponds to the operation NOT and can be used only right after the '=' sign. The parenthesis '(' ')' are used to build the function, where '.' is the AND operator and '+' is the OR operator.

The complex gate compiler produces compact cells with higher performances in terms of spacing and speed than NAND/NOR based conventional logic circuits.


Fig. 34. A compiled complex gate (CARRY cell)

Compiler Syntax

Cell Formula

Inverter out=/in

NAND gate n=/(a.b)

AND gate s=(a.b)

3 Input OR s=a+b+c

3 Input NAND out=/(a.b.c)

AND-OR Gate cgate=a.(b+c)

CARRY Cell cout=(a.b)+(cin.(a+b))

TRANSISTOR SIZE. The default device size is given by the design rules. You may change the nMOS and pMOS width in the option menu before clicking on COMPILE.
IMPLEMENTATION. The p-channel transistors are located at the top of the n-channel transistor net. If the '/' operator has not been specified after the '=' sign, an inverter is added at the right hand side of the compiled cell. That is why an AND gate is compiled as a NAND gate followed by an inverter.

4. Arithmetic Gates

Half-Adder Gate
The Half-Adder gate truth-table and schematic diagram are shown in Figure 34. The SUM function is made with an XOR gate, the Carry function is a simple AND gate. Load the layout design of the Half-Adder through the F3 (eq. to File -> Read) and HADD.MSK sequence.

HALF ADDER

A B SUM CARRY

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

Fig. 34. Truth table and schematic diagram of the half-adder gate (HADD.MSK).

FULL CUSTOM LAYOUT. You may create the layout of the half-adder fully by hand using the XOR gate first by inserting the AND gate layout (Command File -> Insert « AND2.MSK », or Compile « carry=A.B »). Then draw the interconnects between gates. Use the polysilicon layer for short connections only, because of the high resistance of this material. Use metal as much as you can, and Poly/Metal, Diff/Metal contact macros situated in the upper part of the Palette menu to link the layers together.

VERILOG COMPILING. You may use DSCH to create the schematic diagram ; verify the latter with buttons and lamps and generate the Verilog text by using the command « File -> Create Verilog File ». Without using DSCH, you may alternatively use a text editor (NotePad or WordPad), and enter the following VERILOG text.

Fig. 35. VERILOG description of the half-adder gate (Hadd.txt)

Click on the command File -> Compile -> Compile Verilog File. Select the text file created just before by a simple text editor.

Fig. 36. Load the VERILOG description of the half-adder gate (Hadd.txt)
Click on Compile. When the compiling is complete, click on OK. The result is shown below. The XOR gate is routed on the left and the AND gate is routed on the right.

Fig. 37. Compiling of the VERILOG description of the half-adder gate (Hadd.txt)
Now, add two clocks inside label « A » and « B », then add an eye on « Carry » and « Sum ». Click on Simulate in the main menu. The timing diagrams appear and you should verify the truth table of the half-adder. Click on Stop to return to the editor.


Fig. 38. Simulation of the half-adder (HADD.MSK).
Full-Adder Gate
The truth table and schematic diagram for the full-adder are shown in Figure 39. The SUM is made with two XOR gates and the CARRY is a complex gate, as shown below.
FULL ADDER

A B C SUM CARRY

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1


Fig. 39. The truth table and schematic diagram of a full-adder (FADD.MSK file).
You may edit the schematic diagram of the full adder using DSCH. Verify the circuit behavior and generate its corresponding Verilog description. The VERILOG description of the Full-adder is given below (fadd.txt):
module fulladd(sum,carry,a,b,c);

input a,b,c;

output sum,carry;
// internal node

wire sum1;

xor xor1(sum1,a,b);

xor xor2(sum,sum1,c);

and and1(c1,a,b);

and and2(c2,b,c);

and and3(c3,a,c);

or or1(carry,c1,c2,c3);

endmodule

Click on the command File -> Compile -> Compile Verilog File. Select the text file « fadd.txt » shown above. Click on Compile, and on OK at the end of the compilation. In Figure 40, the XOR gates are at the left side of the design while the complex gate is at the right side of the cell.

The simulation of the full-Adder is conducted as follow. First, add a clock on labels « A », « B » and « C ». For clock « A », enlarge the value of the clock in order to slow down the chronogram. The cell is complex and cannot react very rapidly. Do not hesitate to zoom in some parts of the layout to be sure to add the property to the desired label. Then add an eye to « carry » and « sum ». The result is given in Figure 41.

Fig. 40. Compiling of a full-adder described in VERILOG.

Fig. 41. Simulation of a full-adder (File FADD.MSK).