3.5.4SHVC design aspects (2 - done)
JCTVC-O0115 Pipeline and parallel architecture for the SHVC decoder [W. Hamidouche, M. Raulet, O. Deforges (IETR/INSA)]
Reviewed Tues 29th (GJS).
This contribution describes an implementation of the SHVC decoder in a "GPAC" player context. The SHVC decoder is based on the open source software "OpenHEVC", which reportedly implements a conforming HEVC decoder (2x-5x faster than HM decoder). The proposed pipeline and parallel SHVC decoder enables two levels of parallelism. The first level decodes the base layer and the enhancement layer frames in parallel. The second level of parallelism performs the decoding of both the base layer and the enhancement layer in parallel by taking advantage of the HEVC wavefronts and tiles high-level parallel processing features.
Experimental results carried out on a computer fitted with an Intel Xeon processor running at 3.4 GHz reportedly showed that the pipeline SHVC decoder achieves the decoding of 1920x1080 base layer and 2560x1600 enhancement layer at 45 frames per second when using six concurrent threads.
This type of work was suggested to be complementary to that described in O0165, since this one focus on tiles & wavefronts and the other focused on the slice level and CTB level.
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