| 1.1 Aim
The aim of this thesis was to improve the existing 10 Gigabit Ethernet XAUI test system,
which is used for testing 10 Gigabit Ethernet devices at the UNH Interoperability Lab
(IOL). Although the current system has enabled successful testing of vendor products, it
requires several expensive test instruments in addition to a high speed FPGA-based
platform. The FPGA portion of the test system is not easily reprogrammed to facilitate
the addition of new test sequences or the use of triggered selection of special test
sequences based on observed responses of the Device Under Test (DUT). There was also
at one time the desire by the UNH IOL to license its 10 Gigabit Ethernet Test System to
industry partners, and this goal motivated re-design of the test system to eliminate key
elements of intellectual property not owned by UNH.
Although this goal was
subsequently dropped by IOL management, the need to improve the reliability, flexibility
of re-programming, and automated test execution speed of the original test system
remained. These objectives have been largely accomplished through the re-design of the
FPGA portion of the test system while continuing to utilize the same hardware platform
on which the current test system is implemented.
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