Supplemental material to



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Supplemental material to
Growth-in-place Deployment of In-plane Silicon Nanowires
Linwei Yu, 1* Wanghua Chen,2 Benedict O’Donnell,1 Gilles Patriarche,3 Sophie Bouchoule,3 Philippe Pareige,2 Regis Rogel,4 Anne Claire Salaun,4 Laurent Pichon4 and Pere Roca i Cabarrocas1*

1 Laboratoire de Physique des Interfaces et des Couches Minces (LPICM), Ecole Polytechnique, CNRS, Palaiseau 91128, France.

2 Groupe de Physique des Matériaux (GPM), Université et INSA de Rouen, CNRS, Saint Etienne du Rouvray 76801, France

3 Laboratoire de Photonique et de Nanostructures (LPN), CNRS, Route de Nozay, Marcoussis 91460, France

4 Institut d'Electronique et des Télécommunications de Rennes (IETR), CNRS, Université de Rennes 1, Rennes 35042, France


EXPERIMENTAL DETAILS
1) Pattern definition and Si nanowire (SiNW) growth: On top of an n+-Si wafer (0.001 Ohm-cm) coated with a 300 nm thick SiO2 layer, ITO/SiNx patterns were made as illustrated in Fig.1 (c)–(d). First, a thin layer of ITO (~10 nm thick) was deposit by sputtering and patterned by lithography into stripe rows of widths 1~5 µm [Fig.1 (c)]. Then, a SiNx layer (~180 nm) was deposit and channel windows with a width of 2~20 µm were opened (normal to the ITO rows) to serve as guiding edges for the growth of SiNWs [Fig.1 (d)]. Finally, the samples were loaded into a PECVD system, where the in-situ growth and positioning of the SiNWs channels involve:

1) H2 plasma treatment at 250 – 350 oC to reduce the exposed ITO regions to precipitate and form indium catalyst drops [Fig.1 (e)], with H2 flow rate, chamber pressure and RF power of 100 sccm, 5 W and 600 mTorr, respectively; 2) cooling down to 100 oC and depositing a thin layer of a-Si:H with a typical thickness of 50 nm, as indicated in Fig1 (f). Typical plasma parameters are SiH4 flow rate, chamber pressure and RF power of 10 sccm, 2 W and 120 mTorr, respectively; 3) The growth of in-plane SiNWs was activated during annealing at substrate temperature of 300 - 450 oC in vacuum (< 10-6 mbar); 4) Finally, the residual a-Si:H layer around the SiNWs was selectively removed by an in-situ low temperature H2 plasma etching at 100-130 oC, with H2 flow rate, chamber pressure and RF power of 100 sccm, 20 W and 380 mTorr, respectively.



For SEM characterizations, the sample surface was coated by a thin Au layer of ~12 nm. To realize a bottom-gate FET structure, Al electrode contacts were made on the selected SiNWs channels by standard lithography procedures, as illustrated in Fig.2 (d), and annealed in argon gas at 400 oC for 30 min for contact formation, while the n+ c-Si wafer substrate served as a bottom-gate electrode.
2) Atom probe tomography (APT) characterizations: A single SiNW was mounted on a tungsten (W) tip, as seen in Fig. 3(c), and cut in the middle and characterized by APT. During the characterization, an ultra-violet laser (at 343 nm with a power of 4 mW) was used as the pulse source, with the chamber pressure and temperature of 2×10-10 mbar and 80 K, respectively. The depth and lateral spatial resolution of APT is 0.1 nm and 0.3 nm, respectively, with a concentration resolution of 100 ppm.



S.1 SEM images of the guided growth of in-plane SiNWs with diameter down to 40, 28 and 14 nm.



1 Corresponding Email: Linwei.yu@polytechnique.edu; Pere.roca@polytechnique.edu.




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