Limits of 2D



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tarix04.11.2017
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Limits of 2D

  • Limits of 2D

  • 3D-IC Benefits

  • 3D-IC Technology





1D gate to 3D gate

  • 1D gate to 3D gate

    • MOS devices start “3D” in 22 nm technology




Needs for improved protection, but noise margins reduced

  • Needs for improved protection, but noise margins reduced



Needs for improved reliability but reduced operating windows

  • Needs for improved reliability but reduced operating windows





“Evolutionary and revolutionary interconnect technologies are needed to enable migration to 3D”

  • “Evolutionary and revolutionary interconnect technologies are needed to enable migration to 3D”



Georgia-Tech vision of SoC

  • Georgia-Tech vision of SoC



“The integration of 3D technologies will enable performances, form factor and cost requirements of the next generation of electronic” devices

  • “The integration of 3D technologies will enable performances, form factor and cost requirements of the next generation of electronic” devices





3D Packaging contributes to “More than Moore” at a reasonable price

  • 3D Packaging contributes to “More than Moore” at a reasonable price



3D technology enables the integration of ICs fabricated in different technologies

  • 3D technology enables the integration of ICs fabricated in different technologies

    • CMOS, CCD, SOI, Sensor


Improve electronic efficiency

  • Improve electronic efficiency

    • 3D minimizes interconnect parasitic effects
    • 3D simplifies multiple supply voltage distribution
    • 3D reduces package pin count
    • More uniform, high density power delivery


A significant increase in bandwidth

  • A significant increase in bandwidth



A significant reduction in I/O complexity

  • A significant reduction in I/O complexity



A better power efficiency

  • A better power efficiency

    • Smaller wire-length distribution
    • Shorter wires decrease the average load capacitance and resistance and decrease the number of repeaters needed for long wires.
    • The reduced average interconnect length in 3D IC, vs 2D IC, improves the wire efficiency by 15-25 %
    • Active power may be reduced by 25-50%






The HE physisict dream…

  • The HE physisict dream…

    • High Energy Physics requires sophisticated detectors
    • integrating sensors
    • readout electronics.




Higher complexity at lower cost

  • Higher complexity at lower cost

    • Stacking of memories


Interposers

  • Interposers

    • Based on silicon or glass
    • Replace traditional PCB laminate or ceramic technologies
    • Alternative to very large 2D ICs at prohibitive costs
    • Very high density and bandwidth
    • “Bridge” platform between 2D and 3D














Via formation for die to wafer process

  • Via formation for die to wafer process








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