MicroWind manual

Path between Pads and Cells

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Path between Pads and Cells

The « path » command considers the easy editing of a path in one layer only (Fig. 81). The path width can be changed, as well as the alignment to the routing grid. A set of contacts can also be placed at both ends of the path. This command is very useful for VDD and VSS supply drawing and single layer interconnects.

Fig. 81. The path menu and a path example

7. Design Rules

This section gives information about the design rules used by Microwind. You will find all the design rule values common to all CMOS processes. All those rules, as well as process parameters and analog simulation parameters are detailed here.

The evolution of the integrated circuit technology resides mainly in the reduction of the feature size, also called « lithography ». As the chart below (Fig. 82) shows, in 1986, the minimum feature size was around 1.2µm. Ten years later, the lithography had been downsized to 0.25µm. For year 2000, the lithography around 0.12µm is expected for leading edge products such as high-performance micro-processors.





Metal layers

Power Supply


Oxide (A)

Threshold (V)

Typical gate delay (pico-sec)

Microwind design rule file
































































Fig. 82 : Technological trends for MOS devices
As can be noticed, the number of metal layers used for interconnects has been continuously increasing in the course of the past ten years while the power supply decreased due to the reduction of the MOS gate oxide thickness, and thus the lower oxide breakdown voltage. The MOS threshold voltage was also significantly reduced. The overall consequence of this technology scale down is the gate delay decrease leading to higher operating frequencies, although the rapid reduction of the power supply slows down the gain in terms of performances.
Some details about the size and electrical properties of the interconnects are reported in Fig. 83. The metal pitch is following the lithography, but the interconnect thickness is not reduced with the same trend. The cross-section of the interconnect is reduced, leading to a higher resistance per length unit. Starting at 0.18µm, one could replace aluminum by copper due to the lower resistivity of the latter and its much greater ability to drive high currents.


Metal layers

Lower metal

Pitch (µm)

Upper metal

Pitch (µm)

Thickness metal (µm)

Static Resistance


Interconnect Materials

Microwind file







Alu, Sio2








Alu, Sio2








Alu, SiO2








Tu, Alu, SiO2








Tu, Alu, Sio2








Tu, Cu, SiO2








Tu, Cu, SiO2


Fig. 83 : Technological trends for interconnects

Design Rules
The software can handle various technologies. The process parameters are stored in files with the appendix '.RUL'. The default technology corresponds to the ATMEL-ES2 2-metal 0.8µm CMOS process. The default file is ES208.RUL.
To select a foundry, click on File -> Select Foundry and choose the appropriate technology in the list.

r101 Minimum well size : 12 l

r102 Between wells : 12 l

r201 Minimum diffusion size : 4 l

r202 Between two diffusions : 4 l

r203 Extra well after diffusion : 6 l

r204 Between diffusion and well : 6 l

r301 Polysilicon width : 2 l

r302 Polysilicon gate on diff n+ : 2 l

r303 Polysilicon gate on diff p+ : 2 l

r304 Between two polysilicons : 3 l

r305 Poly v.s other diff diffusion : 2 l

r306 Diffusion after polysilicon : 4 l

r307 Extension of Poly after diff : 2 l

r401 Contact width : 2 l

r402 Between two contacts : 3 l

r403 Extra metal over contact:2 l

r404 Extra poly over contact: 2 l

r405 Extra diff over contact: 2 l

Metal 1
r501 Metal width : 3 l

r502 Between two metals : 3 l

r601 Via width : 3 l

r602 Between two Via: 3 l

r603 Between Via and contact: 3 l

r604 Extra metal over via: 2 l

r605 Extra metal 2 over via: 2 l

Metal 2
r701 Metal width: 5 l

r702 Between two metal2 : 5 l

Via 2
r801 Via2 width : 3 l

r802 Between two Via2s: 4 l

r803 Between Via2 and via : 4 l

r804 Extra metal2 & metal 3 over via2: 3 l

Metal 3
r901 Metal3 width: 6 l

r902 Between two metal3s : 5 l

Via 3
ra01 Via3 width : 4 l

ra02 Between two Via3s : 6 l

ra03 Between Via3 and via2 : 6 l

ra04 Extra metal4 and metal3 over via3: 6 l

Metal 4
rb01 Metal4 width: 10 l

rb02 Between two metal4s: 22 l

Via 4
rc01 Via4 width : 4 l

rc02 Between two Via4s : 6 l

rc03 Between Via4 and Via3 : 6 l

rc04 Extra metal4 & metal 5 over via4: 6 l

Metal 5
rd01 Metal 5 width: 10 l

rd02 Between two metal5s : 22 l

rp01 Pad width: 100 µm (lambda conversion depending on the technology)

rp02 Between two pads 100 µm

rp03 Opening in passivation v.s via : 5µm

rp04 Opening in passivation v.s metals: 5µm

rp05 Between pad and unrelated active area : 20 µm

Parasistic Capacitors
Each deposited layer is separated from the substrate by a SiO2 oxide and generated by a parasitic capacitor. The unit is the aF/µm2 (atto = 10-18 ). Polysilicon, Metal and Metal2 generate parasitic capacitors. Diffused layers generate junction capacitors (N+/P-, P+/N). The list of capacitances handled by MICROWIND is given below.
The name correspond to the code name used in ES208.RUL.
CMEBody Metal on thick oxide to substrate 17 aF/µm2

CMEPoly Metal on polysilicon 50

CM2Body Metal2 on thick oxide 13

CM3Body Metal3 on thick oxide 15

CM4Body Metal4 on thick oxide 13

CM5Body Metal5 on thick oxide 10

CM2Poly Metal2 on polysilicon 25

CM2Metal Metal 2 on metal 45

CPOOxyde Poly gate 1500

CPOBody Poly on field oxide 60

CDNDiffp Junction diode Diffn in p-well, surface 420

CDPDiffn Junction diode Diffp in n-well,surface 350

CLDn Junction diode Diffn in p-well, lineic 260 aF/µm

CLDp Junction diode Diffp in n-well, lineic 310 aF/µm

Design Rule File
An example of design rule file ES208.RUL (ATMEL-ES2 0.8µm technology) is given below.



* Rule file for

* Atmel ES2 0.7µm

* CMOS 2-metal


* 23 Fev 97 by Etienne Sicard

* Modified : 6-Jun-97 Res,thick,GDS2, CIF

* : 9-Jun-97 Metal,metal2 capas



NAME Atmel-ES2 0.7µm - 2 Metal


lambda = 0.4 (Lambda is set to half the gate size)

metalLayers = 2 (Number of metal layers : 5)


* Design rules associated to each layer


* Well (1)

r101 = 10 (well width)

r102 = 10 (well spacing)


* Diffusion (12,14)


r201 = 4 (diffusion width)

r202 = 4 (diffusion spacing)

r203 = 6 (border of nwell on diffp)

r204 = 6 (nwell to next diffn)

r205 = 5 (diffn to diffp)

* Poly (11)

r301 = 2 (poly width)

r302 = 2 (ngate width)

r303 = 2 (pgate width)

r304 = 3 (poly spacing)

r305 = 1 (spacing poly and unrelated diff)

r306 = 4 (width of drain and source diff)

r307 = 2 (extra gate poly)

* Contact (16)

r401 = 2 (contact width)

r402 = 3 (contact spacing)

r403 = 2 (metal border for contact)

r404 = 2 (poly border for contact)

r405 = 2 (diff border for contact)

* Metal (17)

r501 = 3 (metal width)

r502 = 3 (metal spacing)

* Via (18)

r601 = 3 (Via width)

r602 = 3 (Spacing)

r603 = 3 (To unrelated contact)

r604 = 2 (border of metal&metal2)

* metal 2 (19)

r701 = 3 (Metal 2 width)

r702 = 3 (spacing)


* Pads (Passiv is 20)


rp01 = 278 (Pad width)

rp02 = 278 (Pad spacing)

rp03 = 13 (Border of Via for passivation )

rp04 = 13 (Border of metals)

rp05 = 63 (to unrelated active areas)



* Thickness of layers


thpoly = 0.7

hepoly = 0.5

thme = 0.8

heme = 1.1

thm2 = 1.2

hem2 = 2.0

thpass = 1.0

hepass = 3.0

thnit = 0.5

henit = 4.0


* Resistance (ohm / square)


repo = 25

reme = 0.075

rem2 = 0.040


* Parasitic capacitances


cpoOxyde = 2300 (Surface capacitance Poly/Thin oxyde aF/µm2)

cpobody = 53 (Poly/Body)

cmebody = 44

cmelineic = 12 (aF/µm)

cmepoly = 52

cm2body = 56

cm2lineic = 10 (aF/µm)

cm2poly = 44

cm2metal = 84


* Crosstalk


cmextk = 50 (Lineic capacitance for crosstalk coupling in aF/æm)

cm2xtk = 80 (C is computed using Cx=cmextk*l/spacing)


* Junction capacitances


cdnpwell = 520 (n+/psub)

cdpnwell = 600 (p+/nwell)

cnwell = 100 (nwell/psub)

cpwell = 100 (pwell/nsub)

cldn = 310 (Lineic capacitance N+/P- aF/æm)

cldp = 820 (Idem for P+/N-)


* Nmos Model 3 parameters



l3vto = 0.8

l3vmax = 130e3

l3gamma = 0.4

l3theta = 0.2

l3kappa = 0.01

l3phi = 0.7

l3ld = -0.05

l3kp = 135e-6

l3nss = 0.07


* Pmos Model 3



l3vto = -1.1

l3vmax = 100e3

l3gamma = 0.4

l3theta = 0.2

l3kappa = 0.01

l3phi = 0.7

l3ld = -0.05

l3kp = 47e-6

l3nss = 0.07


* MicroWind simulation parameters


deltaT = 4.0e-12 (Minimum simulation interval dT)

vdd = 5.0

temperature = 27



* MicroWind name, Cif name, Gds2 n°, overetch for final translation


cif nwell CNWI 1 0.0

cif aarea CTOX 2 1.0

cif poly CPOL 11 0.0

cif diffn CNPI 12 1.0

cif diffp CPPI 14 1.0

cif contact CCON 16 0.1

cif metal CME1 17 0.0

cif via CVIA 18 -0.1

cif metal2 CME2 19 0.0

cif passiv CPAS 20 0.0

cif text text 0 0.0


* End atmel-ES2 0.7µm


8. Program Operation

Getting Started
To get your MICROWIND program started, use the following procedure:
ΠInsert the MICROWIND diskette into drive a:

 Under Windows 95/NT, click on Start -> Execute

Ž Type a :install and press ¿

 Create a shortcut to the executable file « Microwind » and double click on it to

start the software

The software runs only on Windows 95 or Windows NT.

NOTICE : The command line may include two parameters :

  1. The First parameter is the default mask file loaded at initialization

  2. The Second parameter is the design rule file loaded at initialization

Example :
The command « microwind fadd ams06.rul » executes MICROWIND with a default mask file « fadd.MSK » and the rule file « ams06.RUL ».

9. Commands


Click on the Copy icon. Move the cursor to the design window, and delimit the active area with the mouse. Consequently, all the graphics included in this area are copied. The external shape of the copied elements appear. Fix those copied elements at the desired location by a click on the mouse.

Click on Undo to cancel the copy command.


Click on the Cut icon. Move the cursor to the design window, and delimit the active area with the mouse. Consequently, all the graphics included in this area are erased. Click on Undo to fix those elements back into the design.

u A layer is protected from erasing if you remove the tick in the palette twice. In the palette, an empty square to the right of the layer indicates a protected layer.
u A layer is unprotected from erasing if you select it again in the palette. A tick in the square to the right of the layer indicates an unprotected layer.
u One box only can be erased by a click inside that box when the cut command is active. The box is then erased.
See Move to move one box or a group of boxes.

See Stretch to stretch a box.

Cif Out
MICROWIND converts the MSK layout into CIF using a specific interface. The CIF file can be exported to various industrial software. The screen is shown below. The right table gives the correspondence between MICROWIND layers and CIF layers, the number of boxes in the layout and the corresponding over-etch. The over-etch is used to modify the final size of the CIF boxes in order to fit the exact design rules.
Click on « Convert to CIF » to start conversion. Some parts of the result appear in the left window.

Compile one Line
The cell compiler is a specific tool designed for the automatic creation of CMOS cells from logic description. Click on Compile -> Compile One Line. The menu below appears. The default equation corresponds to a 3 input NOR gate. If need one can use the keyboard in order to modify the equation and then click on Compile. The gate is compiled and its corresponding layout is generated.

The first item of the one-line syntax corresponds to the output name. The latter is followed by the sign « = », the optional sign not « / », and by the list of input names separated by the operators AND « . » or OR « . ». If need be, parenthesis can be added. The input and output names are 8 character strings maximum.
The table below shows different examples of cell formulas :
Compiler Syntax

Cell Formula

Inverter out=/in

NAND gate n=/(a.b)

AND gate s=(a.b)

3 Input OR s=a+b+c

3 Input NAND out=/(a.b.c)

AND-OR Gate cgate=a.(b+c)

CARRY Cell cout=(a.b)+(cin.(a+b))

TRANSISTOR SIZE. The default device size is given by the design rules. You may change the nMOS and pMOS width in the option menu before clicking on PILE.
IMPLEMENTATION. The p-channel transistors are located on the top of the n-channel transistor net. If some layout already exists near those icons, the cell origin is moved to the right until enough free space is found. If the '/' operator has not been specified after the '=' sign, an inverter is added at the right hand side of the compiled cell. That is why an AND gate is compiled as a NAND gate followed by an inverter.
Compile a VERILOG description
The cell compiler can handle layout generations from a primitive-based VERILOG description text into a layout form automatically. Click on Compile -> Compile Verilog File. Select a VERILOG text file and click on OK. For instance, the microwind directory contains the « HADD.TXT » file which corresponds to the description of a half-adder.
The menu below appears. If need be modify the transistor sizing and click on Compile. The VERILOG text is compiled into a set of basic gates and its corresponding layout is generated.

Design Rule Checker

The design rule checker (DRC) scans all the design and verifies that all the minimum design rules are respected. Click on the icon above or on Analysis ->Design Rule Checker to run the DRC. The errors are highlighted in the display window, with an appropriate message giving the nature of the error. Details about the position and type of the errors appear on the screen.

To obtain any further information about the design rules, see Chapter 8.

Draw a Box

The « Draw Box » icon is the default icon. It creates a box in the selected layer. The default layer is Poly. If the « Draw Box » icon is not selected, click on it. Then, move the cursor to the display window and fix the first corner of the box with a press of the mouse. Keep pressed and drag the mouse to the opposite corner of the box. Release the mouse and see how the box is created.
The active layer is selected in the palette. The red color indicates the active layer. The tick specifies that all boxes using the layer can be erased, stretched or copied. Removing the tick protects the layer.
Duplicate XY

The command « Duplicate XY » is very useful to generate an array of identical cells such as RAM cells for example. Click on Edit -> Duplicate XY, include the elements to duplicate in an area defined by the mouse, and the following screen appears. In both X and Y, the default multiplication factor is x 2. You may adjust the space between cells. By default, the cells touch each other.

Extract Options
The extraction options are detailed in the menu below. The default extraction includes the removal of redundant boxes (Purge) and the removal of overlaps (Merge). The fast extraction does not handle Purge nor Merge operations.
The MOS level can be chosen between level 1 and 3. See chapter 2 for more details about those models.
Other options concern the computation of lateral capacitances and vertical crosstalk capacitances.

Floating Node
Click on Analysis -> Floating Nodes to scan the layout and detect nodes that might be floating. The navigator gives the list of the floating nodes in the Navigator menu. Click on the corresponding name to locate it in the drawing. A floating node is an interconnect not connected to a diffusion. Floating gates are listed even if they include a clock or pulse property.

Click on File -> Select Foundry. The list of available processes appears. The default design rule file is written in bold characters. Various technologies are available from 1.2 down to 0.12 µm. Click on the rule file name and the software reconfigures itself in order to adapt to the new process.
Click on File ->Print Layout to transfer the graphical contents of the screen to the printer. You can make a copy of the window into the clipboard in order to import the screen into your favorite text editor by pressing +
. In the text editor or in the graphic editor, simply click on « Edit ->Paste » We recommend that you switch to monochrome mode first by invoking the function File -> Monochrom/Color. In that case the layout will be drawn in a white background color using gray levels and patterns.

The library contains a set of predefined layout macros such as contacts, devices and pads. Those cells are built according to design rules, and contain size parameters. To invoke the cell library click on the above icon.

CONTACTS. Contacts such as polysilicon/metal, n-diffusion/metal, p-diffusion/metal and metal/metal2 metal2/Metal3,(etc..) can be obtained here. You may also repeat a number of contacts in X and Y. You may also generate a polarization seal around the contact to create a pad diode protection for example.
Click on Generate Contact. The outline of the latter appears. Then click on the mouse to set this outline in the appropriate place.

MOS. This macro generates either a n-channel or a p-channel transistor. The parameters of the cell are the channel length (default value is given by the design rules), its width, and the number of gates. Once those parameters are defined, the device outline appears. Click on the mouse to place it in the appropriate place.

PADS. It is possible to add various items such as a single pad, a test pad (usually 30x30 µm), or even a set of pads all around and to the layout using the VDD and VSS power rings. In the last case (adding more than one pad), give the number of pads each side of the chip and if need be modify the width of the VDD and VSS tracks.

ROUTING. This command is used to rout interconnects in one metal layer (metal 1 by default) for horizontal tracks and in another metal layer (metal2 by default) for vertical tracks. The appropriate contact is generated automatically. This command is very useful for cell routing using two different metal layers.

PATH. This command is similar to the ROUTING command but it considers only one layer. The path width can be changed, as well as the alignment to the routing grid. A set of contacts can also be placed at both ends of the path. This command is very useful for VDD and VSS supply drawing and single layer interconnects.

BUS. This command generates a set of parallel lines with user-defined layer, width and spacing. This command is useful to build the final routing of a chip.

Measure distance : See « ruler »

MOS device

Click on the icon. The Id/Vd curve of the default MOS (W=20µm, L=L minimum) appears. You can skip to Id/Vg mode to highlight the threshold voltage, or to Id(log)/Vg to see the sub-threshold behavior. You may add measurements by selecting a « .MES » file then skip from NMOS to PMOS and select the size of the device in the lower menu.
Two models can be used :

  • MOS Model 1 (Berkeley Spice)

  • MOS Model 3 (Simplified version of Berkeley Spice)

The effects of the changing of the model parameters can be seen directly on the screen by a click on the little arrows which change the parameter values.

Also, the vertical scale can be altered, as well as some configuration parameters.

Click on View->Measurements to load some measurements together with the simulations in the I/V window proposed above. This command is a short cut to the button « Add Measurement » of the MOS characteristics window.

Move a Box

To move one box, click on the above icon. Using the mouse, create an area which includes the box. Then, drag the mouse to the new location and release the mouse. As a result, the box has been moved the new place. Repeat the same in order to move a set of boxes. To protect a layer from moving , click in the rectangle the palette that is situated on the right side of the layer. This will remove the tick.
File -> New
Click on File-> New in order to restart the software with an empty screen. The current design should be saved before asserting this command, as all the graphic information will be physically removed from the computer memory. No Undo is available to disable the New command.
File -> Open
Click on the icon . In the list, double-click on the file to load. « .MSK » is the default extension that corresponds to the layout files. The CIF files « .CIF » can also be loaded. The appropriate conversion program transforms the input CIF into MSK format.
File -> Insert
The command File -> Insert is used to add a MSK file to the existing files. The inserted layout is fixed at the right lower side of the existing layout. The current file name remains unchanged.
File -> Statistics
The command File -> Statistics provides some information about the current technology, the percentage of memory used by the layout and the size of the layout plus its detailed contents. If the layout has previously been extracted or if you click « extract now », the number of devices and nodes will be updated.

View Node

Click on the icon above or onView -> View Node. Then, click in the desired box in the layout. After an extraction procedure has been carried out, you will see that all the boxes connected to that node. In the case of a large layout, the command may take time. The associated parasitic capacitance and the list of text labels added to the selected boxes are also displayed in a specific window.
Click or View -> Unselect All to unselect the layout.

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