The commercial chip design tools available today are very powerful

The commercial chip design tools available today are very powerful

• The commercial chip design tools available today are very powerful

• However, these tools are highly complex and need long time to learn.

• Teaching hours in Nano-CMOS are decreased

• Physics of semiconductors are exploding in complexity (100-1000 parameters in MOS models)

• Student and engineer diversity must be considered. Gaps in the background knowledge must be addressed

Tools should be used by large number of students at undergraduate level

• Tools should be used by large number of students at undergraduate level

• Design tools should provide intuitive design, simulation and visualization environments

• Design tools should be easily accessible. Most of the work is done out of regular teaching hours (e-learning, project-based..)

• Target course and practical training duration: 15 H

• Target level : Master year 1

Technology scale down, where we come from, where we are (45 nm), where we go..

• Technology scale down, where we come from, where we are (45 nm), where we go..

• A tutorial on MOS devices, based on problem-based learning

• The design of inverters, and a simple ring oscillator, and a small student contest.

• The design of basic logic gates introducing interconnect design, compact design strategies, and impact on switching speed and power consumption.

• The design of analog blocs introducing amplification, voltage reference, addition of analog signals, and mixed-signal blocs

• A design project, e.g. converter, processing unit, OpAmp, radio-frequency block, etc..

User-friendly and intuitive design tool for educational use.

• User-friendly and intuitive design tool for educational use.

• The student draws the masks of the circuit layout and performs analog simulation

• The tool displays the layout in 2D, static 3D and animated 3D

MOS DEVICE

• MOS DEVICE

• Traditional teaching : in-depth explanation of the potentials, fields, threshold voltage, and eventually the expression of the current Ids

• Our approach : step-by-step illustration of the most important relationships between layout and performance.

• Design of the MOS

• I/V Simulation

• 2D view

• Time domain analysis

BASIC GATE DESIGN

• BASIC GATE DESIGN

• Illustration of the most important relationships between layout and performance.

• Design of pMOS

• Design of inverters

• Design of a VCO

• Try to optimize the VCO for highest possible speed

• Improve MOS size

• Change MOS options

• Make the layout more compact

• Keep an eye on power consumption

PROJECT EXAMPLES

• PROJECT EXAMPLES

• engage students in a stimulating learning experience using latest CMOS technologies

• Circuit analysis and optimization using WinSpice

• Combinational and sequential circuit layouts

• ALU Design

• Power amplifier Bluetooth

The VLSI course was evaluated anonymously by the students

• The VLSI course was evaluated anonymously by the students

• UNISA course evaluation questionnaire containing ten core questions and open text response.

• The students rated the course very highly in all the evaluation items.

• The course in the in the top-5 courses offered in engineering in UniSA.

• (off-line: Dr. Aziz won the “top teacher of the year” in Australia 2009)

Answers to questionnaire

• Answers to questionnaire

The best student reports are put on-line on www.microwind.org > Student reports

• The best student reports are put on-line on www.microwind.org > Student reports

• Student works from other institutes and countries are also placed on-line

“From just a few logic gates, we have created a 4-stage binary counter and compiled it into layout. It also gave us the basic concepts to understand the operation of the transistors in order to extract their models.”

• “From just a few logic gates, we have created a 4-stage binary counter and compiled it into layout. It also gave us the basic concepts to understand the operation of the transistors in order to extract their models.”

• “The 24-hours clock project was a good exercise which permitted us to see how it is inside a semiconductor and how it works.”

• “We learned a lot about designing integrated circuit. We faced some practical problems, and tried to solve them or to understand them.”

• “This study allows us to understand the DAC running. In spite of some design problems, we managed to make the DAC work well.”

• “Before doing this project, we hadn’t thought that there are as many ways to realize an amplifier. It’s an area not easy to understand. Each technique has its limit. We tried to optimize our operational amplifier design to maximize the gain.”

Application notes on 90, 65, 45 & 32nm technologies

• Application notes on 90, 65, 45 & 32nm technologies

• Evolution of MOS devices and interconnect performances

• Synthesis of the state of the art (Intel, Samsung, ST-microelectronics, ITRS…)

• Illustration and discussion on technology advances

Application notes on 22 nm and 17 nm technologies

• Application notes on 22 nm and 17 nm technologies

• Introduction of FinFET device

• Introduction to 3D-IC technology & design