Until now, running a processor at a higher frequency was the only way to increase processing capabilities. Unfortunately, this approach has recently reached microelectronics limits. Multi-core (MC) processor technology was introduced a few years ago. It is bringing a smart solution to run several processors in parallel while keeping power consumption under acceptable limits.
MC technology can address many applications. As performance requirements keep growing (demanding applications, growing number of subscribers, higher bandwidth, secured communications, etc.), the telecommunications and networking markets are MC early adopters. They can clearly benefit from the significant improvements brought by MC technology to design an efficient software architecture for telecommunications, network, and security equipment:
The MC architecture allows a flexible distribution of cores between the data plane and control plane and the coexistence of different execution environments (one for fast path and one for slow path and control plane, for instance) on a single chip. On a 16-core processor, for example, a typical application of MC technology for telecommunications equipment is to use several cores to implement an efficient fast path under a multi-core execution environment (MCEE). The remaining number of cores are dedicated to the operating-system (OS) environment (Linux, for instance) implementing the slow path (IP stack) and control plane. The different functions are co-localized in a single MC chip, but distributed over the different cores.
MCEE provides application programming interfaces (APIs) to implement lock free packet processing and optimize memory bandwidth contention. The result is unrivalled performance compared to a standard OS. Although the services provided by such a dedicated environment are limited, the programming model is simpler compared to the previous generation of network processors based on micro-coded architectures. It is therefore easier to provide complete features at the data-plane level.
Built-in hardware features (crypto engines, packet matching engines, and hardware queue for QoS management) can be used for an efficient implementation of time-consuming functions, such as encryption or deep packet inspection.
Standard operating systems also have been ported on MC technology. A slow path and control plane that implement more complex mechanisms can run under a standard OS. However, it requires an efficient multi-processor implementation of the networking stacks to be able to use it efficiently across several cores at the same time.
The MC architecture is by essence scalable and can be used to interconnect different MCs to have, for example, a distributed fast path over several MCs or to deliver high-availability features.
Developing networking software for MC can be perceived as complex because standard software cannot fully benefit from MC improvements. In addition, it requires some long and costly re-design phases for each protocol. One of the key issues to be solved is the integration of the control plane, slow path, and fast path to benefit from the level of performance of the MC technology.
Efficient networking software for MC platforms has to be designed with several key concepts in mind:
Networking software should be specifically designed for MC including an efficient fast-path architecture to make the best use of MC performance according to the number of cores. It also should include a flexible distribution of the control plane/slow path/fast path over the cores as well as a complete synchronization between these three elements.
High-level APIs to interface hardware features, such as crypto-engines or hardware queues for QoS, should be available. In addition, generic features should be fully portable to provide hardware independence.
MC-specific software running under MCEE should be fully integrated with the control-plane OS to provide a transparent solution for applications and maximize the reuse of existing software. Such integration hides MC complexities for applications.
Networking software should integrate a complete and comprehensive set of L2/L3 networking features—each one optimized between the fast and slow paths.
Networking software should be open for extension to ease the integration of differentiating and value-added features.
Meeting these key concepts will significantly reduce time to market for equipment providers to deploy innovative services for fixed and wireless networks. It also will help to meet cost and design challenges for designing telecom/networking applications on top of multi-core environments.
Eric Carmes is founder and CEO of 6WIND. He has more than 15 years of experience in IP standards and architectures and is an expert in current and next-generation IP technologies and protocols. Carmes holds a master of science degree from both INSA (French University for Applied Sciences) and ESE (French Electrical Engineering University). He can be reached at email@example.com.