| 1.3 Organization of Thesis
The second chapter gives an introduction to Ethernet and the development of 10 Gigabit
Ethernet. The objectives of 10 Gigabit Ethernet and the various implementations within
the standard are also discussed in this chapter.
The third chapter discusses in detail the 10 Gigabit Ethernet Attachment Unit Interface
(XAUI). This chapter also covers the different features of Xilinx’s incorporated
embedded PowerPC processor and 3.125Gbps RocketIO serial transceivers that were
used for the development of the test system.
The fourth and fifth chapter discusses the implementation of the Transmit and Receive
process. These chapters introduce the reader to the implementation details of the design.
The chapters also present the implementation issues observed in the design. Finally,
suggestions for future work are provided.
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