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Hellenic Aerospace Industry (GR), University of Patras (GR) Contact Point Duration Dr. Vasileios Tzermpinos 24 months from 1.12.1997 Hellenic Aerospace Industries R&D Division P.O. Box 23 320 09 TANAGRA (Greece) Tel. +30-262-52 537 Fax +30-262-52 170 email hai51@haicorp.com EP 25256 LPGD A Low-Power Design Methodology/Flow and its Application to the Implementation of a DCS1800-GSM/DECT Modulator/Demodulator Summary A top-down design methodology/flow is proposed for power reduction, emphasising on optimisations at the algorithmic and architectural levels with respect to area, time and power. The design flow includes global and local power optimisation techniques and transformations at each design level. At the algorithm level, alternatives are explored in respect of locality, complexity, parallelism, and loop transformations. At the architecture level, the switching activity problem of modules and their interconnections is reduced by techniques like power-down, memory management, clock distribution, and data representation in relation to the statistical features of input signals. At the logic level, further power optimisation may be achieved by reducing the switching activity of the nodes of a logic circuit, by technology mapping, or by multilevel logic transformations. The design flow will be described in a universal way, so that its integration and application to other Design Environments is possible. It will be demonstrated at the example of a GFSK/GMSK MODEM, one of the most critical blocks in the entire baseband signal processing of a multi-mode DCS1800-GSM/DECT terminal.
· To complete the development of a top-down, low power design methodology/flow for DSP applications. · To demonstrate the methods at the example of an integrated GFSK/GMSK Modulator-Demodulator (MODEM) for DCS1800-GSM/DECT applications.
The partners in this project have jointly developed a high-performance 24-bit DSP which is suitable for a multitude of applications, such as decoding the AC-3 Dolby standard for digital TV audio, voice compression, multi-channel echo-cancellation, digital beam forming, etc. This DSP has been fabricated and has been demonstrated in an AC-3 decoder application. The project partners have also been working on the development of low power design techniques aimed at achieving 25% power reduction over designs performed with our current cell-based IC design flow. These techniques are based on the exploitation of local don’t care conditions in multi-level logic circuits and gate resizing to achieve a net reduction in overall circuit power dissipation. A greedy algorithm for low power circuit node optimization using local don’t care conditions has been developed and tested in a simulation environment with encouraging results.
· To apply the developed low power design techniques to the existing 24-bit DSP which is already fabricated · To assess the merit of the mew techniques using experimental silicon through - comparisons of the projected power reduction (in simulation) and actually measured reduction of new DSP; - assessment of the commercial impact.
The objective is to investigate a new micropower wireless data transmission solution over short distance, in the UHF ISM frequency bands (430 and 920 MHz). The micropower transceiver will make use of an original architecture based on the super-regeneration principle. This circuit will be developed by the Electronics Laboratory of EPFL as a monolithic IC. The principle of super-regeneration, which is based on the variation of the start-up time of an oscillator as a function of the signal coupled from the antenna, allows a very simple transceiver architecture, and appears to be particularly suited to micropower applications, compared to classical solutions such as the superheterodyne, the low IF (Intermediate Frequency) or the direct conversion receiver. The present project seeks to take up the basic idea of superregeneration by introducing original analog integrated circuits techniques for low-power performance such as automatic power-down techniques, as well as improved selectivity, sensitivity and cancellation of parasitic radiation compared to a discrete-components solution. The core of the superregeneration system being an oscillator, the receiver and transmitter functions make full use of the same circuit blocks. The whole concept has been validated by simulation. A first version of the core of the receiver has been realised in AMS BICMOS 0.8 µm technology. The superregenerative transceiver will be used in 3 industrial applications which share the constraint of requiring micropower wireless data transmission over short distance: (1) a remote control for vehicle alarms (Transval), (2) wireless computer peripherals (Logitech), and (3) a wireless data transmission system for water counters (Mead Microelectronics). Objectives
Participants EPFL- LEG (CH), Transval SA (F), Logitech SA (CH), Mead sa (CH) Contact Point Duration Dr. Catherine Dehollain 24 months from 01.12.97 EPFL, LEG, ELB Ecublens, CH-1015 Lausanne, (Switzerland) Tel: +41 21 693 69 71 Fax: +41 21 693 36 40 E-mail: catherine.dehollain@epfl.ch ESD-LPD 25403 SOFLOPO Low Power Software Development for Embedded Applications Summary SOFLOPO will develop techniques and guidelines for mapping a specific algorithm code onto appropriate instruction subsets, so that it allows an optimal low-power code execution, for microprocessor architectures used in embedded applications. The power consumption of the code will be evaluated by means of physical measurements, instead of a detailed bottom-up simulation approach, which is unavailable due to the lack of detailed processor models. Upon these measurements, detailed models that relate software code and power dissipation will be established. These models will form the basis of developing code optimization techniques for the purpose of low-energy software execution. Extensions of existing algorithms for Interpreter optimization, that will aim at energy minimization will be developed. This systematic modeling of the relationship between power dissipation and software code will take place for the ARM-RISC processor. An extension of the above methodologies to include DSP processors will follow. These processors constitute a big portion of embedded microprocessors. Except from specific conclusions for each architecture under inspection, general conclusions, applicable to other architectures, within some accuracy limit, will be extracted. The viability of the derived techniques will be demonstrated by their application upon the implementation by DCT- Hellas of the IEEE 802.11 protocol microcode, used in Wireless Local Area Networks. For their full dissemination, the results of the SOFLOPO project will be integrated into software for the power-conscious ARM-RISC and DSP code optimization. This software will be available to interested third parties. It will be also available for free to Universities under a non-disclosure agreement.
Participants University of Patras (GR), Data Communications Technologies-Hellas (GR) Contact Point Duration Dr. Thanos Stouraitis, 24 months from 01.11.97 Department of Electrical and Computer Engineering University of Patras, Rio, 26500, (Greece) Tel: +30 61 997322 Fax: +30 61 994798 E-mail: thanos@ee.upatras.gr EP 25475 COLOPODS Design of a Cochlear Hearing Aid Low-Power DSP System Summary The proposed project reduces the power consumption of the external processor of the LAURA Cochlear Implant system. The Laura Cochlear Implant is an implantable device for the deaf and profoundly hearing impaired that electrically stimulates the auditory nerve fibres. The operation of the internal part of the LAURA cochlear implant system is controlled by an external speech processing system the size of a normal hearing aid. In this speech processor the sound signal is processed into stimulation commands that are transmitted to the internal part. A low power implementation will make operation from standard hearing aid battery cells possible. This will mean a fundamental upgrading of the LAURA cochlear implant system and will allow a stronger position for Antwerp Bionic Systems on the world market. It is expected that the redesign of the cochlear hearing aid Digital Signal Processor in a low power technology will reduce the processor's power consumption by a factor of 10. Through gained know-how and experience in low power optimisation, low power DSP design techniques the speech processing can be further optimised using dedicated processing architectures. ABS has two alternatives for the low power I.C. technology for the actual implementation: a low power, high speed IMEC pilot process and a mainstream PHILIPS process that would be operated at a low voltage yielding a low power, low speed technology. Since both technologies have their own drawbacks and advantages, a pre-study is incorporated in the project to select the most appropriate technology. Objectives
Participants ABS (B) Contact Point Duration Ir Jan Janssen, 16 months from 01.12.97 Antwerp Bionic Systems N.V. Drie Eikenstraat 661, 2650 Edegem (Belgium ) Tel: +32 3 825 26 16, Fax: +32 2 825 06 30 E-mail: jan.janssen@phi.com EP 25476 PAPRICA POWER AND PART COUNT REDUCTION INNOVATIVE COMMUNICATION ARCHITECTURE Summary The PAPRICA project will demonstrate the capability of CMOS technology in the low power RF domain, to achieve a considerable power reduction in wireless terminals. The main goal is to design a new architecture for RF digital mobile communication systems. The novel receiver architecture, called DOUBLE Quasi-IF with early A/D conversion (DQIF), offers a high degree of flexibility, allowing its implementation for a different number of standards, like DECT, PMR (TETRAPOL), and GSM. Since a relevant part of signal processing is performed at baseband instead of high frequency, the architecture offers a reduction in power consumption when compared with other traditional techniques, like the super-heterodyne one. Particular features are i) triple RF to baseband down-conversion, with ii) first down conversion at 150 MHz through a LO at fixed frequency, iii) second conversion of a sub-band of 3 MHz containing the desired channel, iv) third completely digital conversion after delta-sigma band-pass A/D conversion, v) final channel selection performed in the digital domain. Due to the particular conversion technique, the electrical specifications of the most critical blocks will be less demanding, and consequently expected power consumption will be very competitive. Project Objectives
Participants ATMEL ES2 (F), IST (P), Matra Communication (F) Contact Point Duration Ben Altieri 30 months from 1 August 1997 Atmel ES2 (France) Tel: +33.442536194 Fax: +33.442536001 E-mail:baltieri@es2.fr EP 25485 ALPINS Analogue Low Power Design for Communications Systems Summary The ongoing trend towards reduced supply voltages of mobile and cordless systems is mainly driven by the need to implement their digital part in modern sub-micron technologies, but it introduces serious problems for the design and verification of analogue circuits. It is the strategy of this project to reduce the minimum required supply voltage of a typical analogue signal processing circuit by focusing on the design methodology of its most critical blocks. In this way, the well-established gm-C filter technique will be optimised for low-voltage operation, new A/D- and D/A- converter concepts will be investigated and the recently developed log-domain filter technique will be brought to commercial use. This filter principle is especially well suited for low-voltage low-power applications, since it represents internal signals by instantaneously compressed voltages, while maintaining an over-all linear transfer function. Innovative and aggressively optimised circuits require also a more profound way of design verification. Therefore, a recently developed Formal Verification Tool will be implemented in the design environment and used for checking the new designs. For ensuring a timely return of investment, a DECT and a GSM handset were chosen as demonstrators for this project.
Participants Siemens AG (D), Siemens EZM (A), Univ. Hannover (D), EPFL (CH) Contact Point Duration Dr. Rudolph Koch 24 months from 16.11.97 Siemens Semiconductor Group HL SP E MS D-81541 Munich,(Germany) Tel: +49 89 636 24048 Fax: +49 89 636 23649 E-mail: rjkoch@scn.de EP 25518 DABLP Low Power Exploration for Mapping DAB Applications to Multi-Processors Summary A channel demodulator and decoder IC for Digital Audio Broadcast (DAB), called DABchic, has been designed by Philips. This IC has a great relevance for near future markets in the digital automotive and handheld DAB terminal segment. IMEC has developed a unique low power system exploration methodology (ATOMIUM), that concentrates on algorithm and architecture transformations at a high abstraction level, and which will be applied to this application. The result will be an alternative architecture, which will be analysed by comparing the power consumption of the new design with the existing one. The power dissipation should be reduced by at least a factor of three. The direct result will be a low-power architecture to be used later in the next generation DAB channel decoder IC, marketed by Philips Semiconductors. The analysis of the result will lead to a further improvement of the ATOMIUM methodology and the supporting system exploration tools. That methodology will be used in the future for IC-architecture designs. In this consortium IMEC delivers the methodology so it becomes available for the Philips design centres. IMEC on the other hand improves the methodology by using the industrial experience. Objectives
The main results of this project will be: · A DAB channel decoder architecture with reduced power consumption; · Proof of the impact of the ATOMIUM methodology; · Refined and extended ATOMIUM methodology and supporting tools Participants Philips (NL), IMEC (B) Contact Point Duration Ir. Paul Lippens, 36 months from 01.11.97 Philips research laboratories Prof. Holstlaan 4 (WAY 41), 5656 AA Eindhoven, (The Netherlands) Tel: +31 40 27 44346 Fax: +31 40 27 44657 E-mail: lippens@natlab.research.philips.com EP 25519 DESCALE Design Experiment on a Smart Card Application for Low Energy Summary The market of smart cards is booming and the European semiconductor industry has a firm lead in the development and production of so-called smart card controllers. From a technology point of view, there are two important trends. Primarily, more and more functionality is added on-chip, requiring more computational power. Both the associated extra energy consumption and the extra heat removal (plastic is a poor heat conductor) are major challenges. Secondly, a large growth is expected in the market for contact-less cards, respectively dual-interface cards. Those cards collect energy from the electro-magnetic field applied to it from some distance. Here it is also critical to lower the peak current consumption. DESCALE, a Design Experiment on a Smart Card Application for Low Energy, proposes the application of the highly innovative handshake technology to address both issues, aiming at some 5 times less power and some 10 times smaller peak currents compared to synchronously operated solutions. The required technologies are all represented in the consortium, so are the means to exploit the results. DESCALE can contribute to strengthen the European leadership in smart cards.
The so-called Universal Serial Bus (USB) is a fast, bi-directional isochronous, low-cost, dynamically attachable serial interface for connecting a wide range of peripherals like telephone/fax/modem, answering machines, scanners, keyboards and mice to PCs. This new standard developed by Compaq, DEC, IBM, Intel, Microsoft, NEC and Northern Telecom is rapidly gaining acceptance across the entire PC industry. All existing USB interface devices are implemented in 3 layers: the electrical interface handled by dedicated analogue hardware, the low-level protocol layers implemented in dedicated digital circuits, and the high-level protocol layers implemented in software. An implementation of all protocol layers in software would be valuable in terms of cost, flexibility, and versatility. In existing USB devices, however, the low-level protocol layers are implemented in hardware, since most available 8-bit microprocessor cores consume more power than available or provide only a fraction of the required processing speed. In the meantime it was shown that CSEM’s CoolRISC microprocessor cores provide already 2/3 of the required processing speed (25 MIPS in 0.5u CMOS technology, while 36MIPS are needed) within the defined power constraints. To reach the USB specifications, critical groups of USB instructions will be implemented in dedicated circuits and integrated as peripherals to the CoolRISC microprocessor core, such that they can be executed in a single microprocessor instruction.
· A software-based low-speed USB device will be developed based on low-power 8-bit microprocessor cores such as CSEM’s CoolRISC. · This device will be integrated in Logitech’s USB mice.
The goal of SALOMON is the development of a design flow that allows a system-level exploration of mixed analog-digital telecommunication ASICs. Such exploration will allow high-level architectural trade-offs between an analog and a digital implementation of a given functional block in order to obtain the lowest overall power consumption. The design flow will allow system designers to simulate architectures by making use of high-level models of the circuits. Together with the high-level simulations, the overall power consumption will be monitored. To this purpose, high-level power estimators will be developed in this project for the different analog and digital blocks that are used in the examples. Today analog-digital partitioning is typically performed in a heuristic manner by an experienced system designer and it is often strongly based on previous designs precluding the investigation of novel architectures that may consume less power. In order to make such system-level architectural explorations feasible without designing every sub-block down to the transistor level, the system designer must be able to simulate the entire system architecture at a behavioural level in order to verify the functionality and the performance. Existing simulation tools are not satisfactory to this end. In this project a new high-level design flow for mixed-signal telecom ASICs will be developed based upon the combination of system-level behavioural performance simulation and power estimators. This general design flow could be implemented by means of a number of different software tools for simulation. In this project, one particular prototype implementation will be realised in order to illustrate the feasibility of the general design flow. Objectives
Participants IMEC (B), K.U.Leuven (B), alcatel-mietec (B) Contact Point Duration Dr. Piet Wambacq, 36 months from 01.10.97 IMEC Kapeldreef 75, B-3001 Heverlee (Belgium) Tel: +32 2 16 281 223 Fax: +32 2 16 281 515 E-mail: wambacq@imec.be EP 25702 I-MODE Low Power RF to Baseband Interface for Multi-Mode Portable Phones Summary The main objective of I MODE is to raise the level of integration in a DECT/DCS1800 transceiver, by implementing the necessary analog baseband low-pass filters and data converters in CMOS technology using low power techniques. The proposed work is closely related to and complements the OCMP Esprit Project (24123) and the ASPIS Esprit Project (20287). OCMP undertakes the development of a direct conversion transceiver for DECT/DCS1800 modes in a bipolar technology, whereas ASPIS undertakes the development of the baseband processing (DSP) function in a CMOS process for DECT/GSM/DCS1800 modes, operating from a 3V supply voltage. In the I-MODE project, the required filters and data converters (not covered in the OCMP or ASPIS Projects) will be implemented, using low-power-effective techniques, such as current-mode, in a CMOS technology. The overall gain in reduced complexity, area and power consumption will be direct for the end product. As a matter of fact, the proposed action is an essential step towards a true one-chip system. Moreover, the use of low-power design methods can contribute to further lowering the power consumption profile for the end product. Objectives
Participants INTRACOM (GR); INSTITUTE OF COMMUNICATIONS AND COMPUTER SYSTEMS-NATIONAL TECHNICAL UNIVERSITY OF ATHENS (GR) Contact Point Duration Mr. Dimitris Dervenis 18 months from 01.12.97 INTRACOM S.A. 19,5 km Markopoulou Ave 19002 Peania, (Greece) Tel: +30 1 6860456 Fax: +30 1 6860312 E-mail: dder@intranet.gr Web: http://www.intracom.gr EP 25710 CRAFT CMOS Radio Frequency Circuit Design for Wireless Application Summary The main objectives of the project are to develop low power and low voltage key RF blocks for highly integrated personal communication terminals and to derive a design methodology for such RF blocks based on the used CMOS technology. This Design Experiment is aimed on advanced architecture and circuit design to allow single chip integration of the base-band and RF section in CMOS technology for 2nd and 3rd Generation Mobile and Wireless Systems using the 900MHz and 2GHz band. The main areas of application for the developed circuits are for example the UMTS (W-CDMA, TD-CDMA), GSM, DECT and FLEX paging standards. By designing, building and testing functional silicon prototypes, enhanced technologies for manufacture and assembly are to be developed in the field of advanced low power CMOS circuits. The prototypes are developed in three steps, component level, block level and system level, and are designed to serve as electronic building blocks in real products in wireless and mobile communications applications. Furthermore, the technology is considered to be suitable for the design of subsystems in the market segments of consumer products, automotive and other industrial applications.
· Advanced CMOS RF circuit design including blocks such as LNA, downconverter mixers & phase shifters, oscillator and frequency synthesiser, integrated filters, delta sigma conversion, power amplifier, etc. · Development of novel models for active and passive devices as well as fine tuning and validation based on first silicon fabricates; · Analysis and specification of sophisticated architectures to meet in particular low power single chip implementation ; · Individual block design, simulation, and evaluation against silicon prototypes; · Exhaustive system validation based on a complete prototype for a dedicated system; · Functional prototypes based on applications for wireless and mobile communications.
OCTAL has developed and is presently commercialising a PCBIT board which plugs into the PC's ISA bus and allows an ISDN interface. The current PCBIT board uses off-the-shelf components based on the Siemens chipset. The objective of this project is to redesign this board in a PC-Card format with a PCMCIA interface so that the portable PC market can be targeted. Essential for the success of a product in the portable market is its low power consumption. We propose to design an ASIC to integrate much of the functionality of the off-the-shelf components. We expect to achieve significant power savings by this process alone. Moreover, we plan to explore some power management techniques to further reduce power consumption. Objectives · Design of a PC-Card board that implements the PCBIT interface; · Integrate levels 1 and 2 of the communication protocol in a single ASIC; · Incorporate power management techniques in the ASIC design: - system level: shut-down of idle modules in the circuit, - gate level: precomputation, gated-clock FSMs; · Evaluate the impact of the different power reduction methods used; · Promote the design methodology and design experiment results. Participants INESC (P), Octal (P) Contact Point Duration Prof. José C. Monteiro, 18 months from 01.11.97 IST / INESC Rua Alves Redol, 9 - Sala 134 (Portugal) Tel: +351 1 310 0283 Fax: +351 1 314 5843 E-mail: jcm@inesc.pt EP 26530 ABACUS Active Bus Adaptor and Controller for remote UnitS Summary In the area of electronic systems for satellites and spacecrafts, where LABEN mainly operates, the demand for an increasing number of channels, while maintaining the same power consumption and system volume, together with the availability of new rad-hard technologies imposes fully integrated solutions. Objective of this design experiment is the development of a mixed-signal ASIC, using 0.8 µm TEMIC SOI technology, that implements an analog-digital interface between the spacecraft On-Board Data Handling (OBDH) bus and the Remote Terminal Units (RTUs). The main characteristics are: · implemention of an analog/digital interface between the spacecraft On Board Data Handling (OBDH) subsystem bus and the satellite Remote Terminal Units (RTUs); · Provision of the RTUs with a non-corrupted data flow (as happens in case of multiple loads on the bus or in case of cross-talk phenomena); · Provision of synchronisation detection and clock period recovery; · Interface the ESA-OBDH data bus in full compliance with the TTCB-01 OBDH protocol. The device has to withstand a wide range of radiation environments, so it has to be radiation hardened. Objectives · To extend design know-how by acquiring the capability to design and manufacture mixed analog-digital components with advanced technologies and state-of-the-art design tools. · To derive design requirements and final design specifications of the device. · To perform the detailed design phase including design and simulation of the functional blocks, performing transistor/gate-level implementation of the functions and simulation allowing also the validation of the high level models. Two iterations are foreseen for this phase. · To produce prototypes of the device. Two iterations are foreseen for this phase.
Equipment Assessment EP 20305 EMW Evaluation of a Highly Productive Computer-controlled Microwave Barrel Ash System for IC Fabrication Summary The performance of the Technics Plasma microwave barrel asher "Plasma-Processor 300-Autoload" is to be assessed in the IC manufacturing line of SIEMENS Bauelemente, Villach. The assessment is to show that the Technics Plasma barrel asher offers the advantages of both barrel (high wafer throughput, low cost of ownership) and single wafer ashing systems (low degree of radiation damage). Objectives · To evaluate and demonstrate high availability and throughput, and low cost of ownership of the barrel asher. · To evaluate substrate surface and gate oxide damage and compare with single wafer ashing systems for different IC process technologies. · To carry out a final equipment test under full production conditions in the SIEMENS Villach production line. Participants Siemens Bauelemente (A); Technics Plasma (D); ZMD (D). Contact Point Duration Michael Schwark 12 months from 08.12.95 SIEMENS Bauelemente Siemensstr. 2 A-9500 Villach (Austria) tel: +43 4242 305 524 fax: +43 4242 305 401 EP 20331 SIDOSI Single Wafer Highly Doped n+ and p+ Amorphous and Polysilicon Summary The performance of the ASM International Paragon single wafer polysilicon deposition system and process are to be assessed, improved and compared with batch systems. The assessment will be on 200 mm silicon wafers. Specifications for 300 mm processing will also be established. Objectives · To evaluate the Paragon single wafer deposition system and a deposition process for heavily p+ and n+ doped amorphous and polysilicon thin films on technical, technological and productivity merits. · To give special emphasis to throughput and cost of ownership of the deposition system and to reactor memory phenomena in connection with reactor cleaning and wafer surface preparation. · To focus on process parameters such as uniformity and reproducibility of film thickness, resistivity and grain size. · To compare costs of single wafer and batch furnace processing. · To provide specifications for 300 mm processing in addition to the assessed 200 mm capabilities of the ASM I deposition system. Participants Gressi (F); ASMI, (NL); Motorola (UK); SGS Thomson (F); Philips (NL). Contact Point Duration Daniel Bensahel 12 months from 01.12.95 GRESSI (CNET) BP 98 F-38043 Meylan (France) tel: +33 76 764140 fax: +33 76 903443 E-mail: bensahel@cns.cnet.fr EP 20390 FORCEFILL Assessment for 0.5 micron contact/via plug technology (Al/0.5%Cu) in a high volume production environment Summary The performance of the Electrotech SIGMA 204 FORCEFILL cluster tool is to be assessed for 0.5 micron contact/via plug technology (Al/0.5%Cu) in the high volume production environment of Texas Instruments, Freising Germany. The advantages of this aluminium FORCEFILL technology over the presently employed tungsten plug and aluminium process has to be demonstrated under manufacturing conditions. The complete metalisation process sequence is: Sputter etch - Ti/TiN - Al/0.5%Cu - FORCEFILL. Objectives · To evaluate performance and cost benefits of the new metalisation technology over the tungsten plug/ aluminium process. · To evaluate the sputter etch - Ti/TiN processes which precede the aluminium deposition and the FORCEFILL process. · To assess and improve the overall equipment performance in a high volume 0.5 micron BICMOS production line Participants Texas Instruments (D); Electrotech (UK); Ericsson (S). Contact Point Duration Leo Stroth 13 months from 01.12.95 Texas Instruments Deutschland Freising Wafer Fab Haggertystr. 1 D-85350 Freising (Germany) tel: +49 8161 804070 fax: +49 8161 804835 EP 20445 CAME Cleaning Assessment in a Mini-Fab Environment Summary The "Chamber-Flow" acid wafer cleaning equipment of SAPI provides an ideal capability for an ASIC mini-fab, such as ELMOS or ZMD, to break away from the conventional robotic wet bench acid cleaning systems, with their high operating costs and over-capacity (1000 wafers/hour), and to use the appropriate capacity of a smaller modular system. Several other advantages, like small footprint, complete air-free "dry-to-dry" process and "piston-effect" rinsing bring advantages over robotic wet benches. Objectives · Assess SAPI "Chamber-Flow" acid pre-furnace in ELMOS new 150 mm fab-line. · Establish and meet target specification for the quality of the cleaning process in terms of particles (<0.05/cm2 at 0.3 micron ), metal contamination (<1.0 x 1010 atoms/cm2 for common metals), and surface roughness (<0.5 nm over 100 x 100 micron. · Establish cost effective, "Caro"-HF-last, cleaning process to above specification as first step. · Establish "High-Rel", highest quality, cleaning process to improved specification as second step. · Correlate cleaning efficiency with actual yield on reliability data from running production. · Characterise the "Chamber-Flow" in terms of CoO, uptime (>95%), MTBF (>500 Hrs), MTTR (<5 Hrs), reproducibility and safety. Participants: ELMOS GmbH (D); Sapi (F); ZMD (D); FhG-IMS (D). Contact Point: Duration: Volker Gruber 15 months from 01.12.95 ELMOS GmbH Joseph-von-Fraunhofer Str. 9 D-44227 Dortmund (Germany) tel: +49 (0)231-7549-232 fax: +49 (0)231-7549-149 E-mail: vgruber@elmos.de EP 20628 CICDIP Hot Cluster for Integrated Vapour Phase Cleaning and Processing of Dielectrics and In-situ Doped Polysilicon Summary The performance of a four port hot cluster delivered by ASMI (platform and CVD modules) and by AST (RTP modules) will be assessed at SIEMENS in Munich. The final goal is to demonstrate technological superiority of clustered single wafer processing of very thin films over batch processes. This should lead to competitive cost of ownership figures even with lower throughput for single wafer processing. Objectives · To establish sequential processes including rapid thermal clean (RTC), DRAM or EEPROM stack (Rapid Thermal Oxidation/Nitration: RTO/N) and rapid CVD of doped poly or nitride (RTCVD). · To examine technical processes, equipment economics (CoO) and reliability for the hot processing cluster-tool. · To compare technological performance and economics of the cluster tool with standard batch processing. Participants Siemens (D); ASMI (NL); AST (D); AMS (A). Contact Point Duration Alexander Gschwandtner 18 months from 01.06.96 SIEMENS (D) Otto-Hahn-Ring 6 D-81739 Munich (Germany) tel: +49 89 636 45067 fax: +49 89 636 48666 EP 25470 PLASMON Assessment of advanced plasma diagnostic tools for in-situ process control and monitoring Summary To evaluate different advanced in situ plasma control tools. The assessment will be carried out on production tools used for 0.25 m technology on 200 mm wafers. In situ monitoring of every product wafer is the key to reducing production time and costs. The use of plasma diagnostic tools helps to avoid misprocessing and wafer scraps. Furthermore, cleaning procedures and chamber conditioning can be optimised in order to increase wafer throughput. Objectives
Participants Siemens AG (D); SGS Thomson (F); Smst (D); Gressi (F) Contact Point Duration Ferdinand H. Bell 15 months from 15.09.97 Siemens AG HL CPS 3 D-81730 Munich (Germany) tel: +49 89 636 50435 fax: +49 89 636 44236 E-mail: ferdinand.bell@hlistc.siemens.de EP 20747 EDUSA European Deep-UV Stepper Assessment Summary The overall goal of this SEA project is to perform an in-depth assessment of the ASM-L PAS 500/300 deep-UV Wafer stepper for the volume production of 0,25 micron CMOS devices and to explore its potential for 0,18 micron geometries. The assessment site is at IMEC, while industrial users from Europe, the USA, Korea and Taiwan will be involved in the assessment. The project should result in the definition of industrial specifications for future deep-UV steppers, thereby strengthening the world-wide market position of the European equipment maker involved. Objectives · assessment of the capabilities of a newly developed deep-UV stepper from ASM-L (PAS 500/300) for the volume production of 0,25 micron CMOS integrated circuits; · evaluation of the stability of key lithographic parameters, such as, resolution, depth of focus, exposure latitude and proximity effects; · study of lens heating effects; · comparative study of the image sensor focus monitoring technique with alternative techniques; · in-depth study of reliability issues such as mean time between failure (MTBF), mean time to repair (MTTR), mean time between incident (MTBI); · analysis of cost of ownership in comparison with i-line steppers, taking into account capital investment, environmental issues, operational cost, material consumption and total installed wafer capacity; · definition of updated specifications for future deep-UV steppers; · initial evaluation of the PAS 500/300 performance for 0,18 micron CMOS technologies. Participants IMEC (B); ASML (NL); Siemens (D); Philips (NL); GPS (UK); AT&T (E); National Semiconductor (USA); TI (USA); AMD (USA); TSMC (Taiwan); Goldstar (Korea). Contact Point Duration Luc Van Den Hove 18 months from 01.06.96 IMEC Kapeldreef 75 3001 Leuven (Belgium) tel: +32 16 281324 fax: +32 16 281214 E-mail: vdhove@imec.be EP 23928 OPTIMA Optical Proximity Techniques in Microelectronics Applications Summary Optical lithography is a key technique used in semiconductor manufacturing. Strong efforts are being made worldwide to drive it to its technical limits in order to postpone the inevitable introduction of non-optical techniques. Optical Proximity Correction (OPC) is a technique which will make it possible to extend the practical resolution limits of existing exposure tools by at least one technology generation. The necessary OPC tools will be developed and evaluated under OPTIMA. Objectives · The overall goal of OPTIMA is to demonstrate the effectiveness of proximity corrections in a production environment for both memory and logic applications. · To develop a commercially available fast software tool which generates fully automatically a proximity corrected IC design with maximum CD variation due to proximity effects not more than 5% of the target dimension. · To produce test masks for proximity parametrisation, demonstration masks for logic and memory applications (total dimension control better than 70 nm), and masks to investigate the resolution limits when applying OPC in combination with other enhancement techniques (total dimension control better than 50 nm). · To assess the economical impact of the introduction of OPC taking into account that prices of proximity corrected reticles will be close to those of embedded PSM. Major results of the first project year. Software and Simulation The first available versions of the OPC correction software are based on a rule-based correction strategy. Using a rule-based approach the CPU time needed for correction is kept to a minimum. The table with rules used for correction can be filled with both experimental as well as simulated data. The OPC software is integrated into the existing SIGMA-C 'CAPROX' postprocessor environment. The users within the consortium are testing the software and provide feedback on performance Mask Making and Implementation. Using the available production facilities, a number of test masks have been generated for the parametrisation of the proximity effects. These test masks include electrical measurement structures that allow fast and efficient data collection over the stepper image field. The dimension control on these masks is in the order of 30nm (3) for the uniformity and 50nm variation in the target dimension. Further improvement is expected from the process enhancements studied in the project. For testing new maskwriters and processes, a test pattern has been designed which is a combination of the structures used for parametrisation and OPC corrected structures. The pattern enables the testing of the resolution, throughput and processing aspects of the maskmaking process. Using the pattern, a number of new high-resolution maskwriters have been evaluated. From the test results an overview of the present and next generation maskwriter capabilities will become available. In Figure 1 SEM photographs of corrected structures are depicted. The structures have been generated using the Leica VB6 and a dry chrome etch process (left) and the EBMF tool using dry etched MoSi (right) and indicate the ultimate resolution capability available within the project.  
Figure 1 Mask with OPC corrected structures. In parallel with maskwriter evaluation and optimisation, chrome etching, resist technology and inspection are studied to achieve the performance required for OPC masks generation.
To use OPC effectively the printing and etching process are characterised in terms of their contributions to the proximity effect. Experimental data (resist and electrical measurements) and simulation are used. In order to benchmark the available OPC software programs, a comparison of the commercially available packages was made in two steps: First, all available OPC tools were reviewed according to their published specifications and roadmaps. Second, a subset (three tools) was selected for more throrough investigation. General features and handling of large data volumes ("load test") were investigated, and the correction efficiency was tested by the exposure of test wafers with corrected and un-corrected designs.
At the project start, high end photomask substrates were produced by Japanese suppliers only, who also dominate the high end photomask blank market. LAPS aims to establish a European source of substrates and blanks, which meet the requirements of 193 nm excimer laser exposure, 0.18 µm process technology, and 300 mm wafer size. Objectives To develop and evaluate 6”x6” substrates for 0.35 µm processing. To develop and evaluate 7”x7” substrates for 0.35 and 0.25 µm processing taking into account material resistance to 248 nm excimer laser radiation damage. To develop equipment and technology for large area substrates (9”x9”), which includes the process steps melting and squaring, and with respect to only technology development (using commercial equipment) includes process steps like slicing, lapping, polishing and cleaning. To develop large area photomasks material for production which is resistant to radiation damage at 193 nm exposure wavelength (for 0.18 µm technologies and beyond).
Evaluation by Siemens of 6” blanks produced by Robotron with substrates provided by Sico indicated the following technological level: state-of-the-art results for all samples checked could be achieved for all parameters with the exception of defect density specification, which was fulfilled only by 3 out of 5 samples. Robotron, as reaction to the above results, has completed upgrading of the cleaning procedures. Improvements concern both handling and hardware used and have been confirmed by tests. Complete blanks will be produced as a next step. First improvements to the quartz melting technology resulted in bigger diameters and lengths of the raw glass ingots than achieved previously. Other relevant parameters remained the same or also improved. Participants At project Start: SICO (D); TBS (A); ROBOTRON (D); SIEMENS (D); IPTH (D) Changes: (actual situation at 28.1.98) TBS renamed to TBP; ROBOTRON taken over by Schott Glaswerke Mainz under firm SCHOTT ML GmbH (retrospectively from 1.1.1998, but not yet in effect); SICO’s business sections involved in this project also taken over by Schott Glaswerke Mainz under firm SCHOTT ML GmbH (retrospectively from 1.1.1998, but not yet in effect) Yüklə 1,25 Mb. Dostları ilə paylaş:
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