Fast, Interconnected and Efficient devices, for frontier exploitation in R

INtelligent, Fast, Interconnected and Efficient devices, for frontier exploitation in Research and Industry
Funding Scheme: FP7-PEOPLE-2012-ITN
Grant Agreement number: 317446
Project acronym: INFIERI

DELIVERABLE NAME: 3D Very Deep Sub Micron CMOS demonstrator with basic interconnect technology: Goals of this study & application
DELIVERABLE REF. N°: WP 2.1
WORK PACKAGE: 2
NATURE OF THE DELIVERABLE: R= Report, P = Prototype, D = Demonstrator, O = Other
BENEFICIARY(IES) CONTRIBUTOR(S): CNRS
AUTHOR(S) NAME(S) & EMAIL(S): M. Vignetti as ESR2 ([e-mail]), F. Calmon ([e-mail]), R. Cellier ([e-mail] ) P. Pittet ([e-mail]) , L. Quiquerez ([e-mail]) , A. Savoy-Navarro ([e-mail])
DELIVERY DATE FROM ANNEX 1: M12
DISSEMINATION LEVEL: RE, CO
PU = Public N/A IN THE INFIERI CONTEXT
PP = Restricted to other programme participants (including the Commission Services) N/A IN THE INFIERI CONTEXT
RE = Restricted to a group specified by the consortium (including the Commission Services) HIGHLY SUGGESTED IN THE INFIERI CONTEXT
CO = Confidential, only for members of the consortium (including the Commission Services) HIGHLY SUGGESTED IN THE INFIERI CONTEXT


Abstract

The development and optimization of position sensitive detectors is of crucial importance especially in the vertex tracking applications for HEP experiments, where both very high spatial resolution and noise immunity are required in the position measurement near the interaction point (IP). Another crucial aspect is the reduction of material budget caused by power dissipation of on-detector Front-End Electronics (FEE), cooling and cabling systems. Several R&D’s on new pixel technologies address these issues within a strong competition. This WP2 activity focuses on a new pixel sensor technology, its associated FEE and low material budget highly integrated sensor and FEE. An innovative device based on silicon avalanche structures and exploiting the concept of coincidence detection was proposed for the first time [1] as “Avalanche Pixel Sensor” (APiX) and further developed [2] by members of this ITN.

Work achieved: APiX concept

The APiX concept consists of a pair of vertically aligned silicon diodes operated in Single Photon Avalanche Geiger mode (Fig. 1).

Fig. 1 Conceptual structure of an APiX sensor [2]

Figure 2: schematic structure of an APiX sensor. The avalanche cell consists of a reverse bias diode and a quenching element [1]

Each diode is connected to a quenching resistor (Fig.2) and is reverse biased well above the breakdown voltage so that an electron generated inside the depleted region of the junction can trigger an avalanche process, giving rise to a macroscopic electrical signal. The breakdown is then promptly quenched thanks to a negative feedback produced by the quenching resistor [1] (or, more generally, a quenching element). It is worth noting that despite of the small thickness of the sensitive material, i.e. the junction depleted region, the large charge amplification produced by the controlled breakdown process provides a strong enough electrical signal which overcomes the need of any analog amplification stage. In the APiX concept, the path of an ionizing particle through the pair of vertically aligned cells triggers a breakdown processes in each cell, producing two substantially coincident electrical signals.

The coincidence of these two signals is processed by an in-pixel fully digital read-out electronics making possible the realization of a position sensitive pixel system suitable for vertex tracking applications [1].

The goal in INFIERI WP2 has been to study and develop an APiX demonstrator for further proof of feasibility and performances by using a moderate degree of integration because constraint on having a cheap prototyping device due to lack of funds for applying the most advanced Very Deep Submicron CMOS 3D and interconnect technologies. In order to reduce tape-out costs as much as possible WP2.1 developed the concept of two identical chips by flip-chip technique after having flipped and 90-rotated the upper one. Depending on the chip surface management two solutions can be obtained: (Fig.3 a and b).

a)

b)

Figure 3: Concept of the new proposed 3D assembly by means of flip chip technique

Related dissemination: Talks

1. 
   Vignetti M., "Development of Novel Pixel Sensors based on 3D CMOS technology for tracking devices", 4th "Intelligent Signal Processing for Frontier Research and Industry” (INFIERI) Workshop – NIKHEF, Amsterdam (The Netherlands), December 10-12, 2014
   
2. 
   Vignetti M., “Development of Novel Pixel Sensors based on 3D CMOS technology for tracking devices,” 5th INFIERI workshop, CERN, April 27-29 2015  
   
3. 
   Vignetti M., Calmon F., Cellier R., Pittet P., Quiquerez L. and Savoy-Navarro A., ”Preliminary simulation study of a coincidence avalanche pixel sensor", INFIERI 2nd International School on Intelligent Signal Processing for Frontier Research & Industry, 14-25 July 2014, Paris, France, Proceedings published in Journal of Instrumentation, Vol. 10 (C06007), June 2015, doi:10.1088/1748-0221/10/06/C06007
   
4. 
   Vignetti M., Update on the development of Novel Pixel Sensors based on 3D CMOS technology, 6th INFIERI workshop, Pisa, October 27-29 2015
   
5. 
   D’Ascenzo N. et al. “Silicon avalanche pixel sensor for high precision tracking,” J. Instrum., vol. 9, no. 03, Mar. 2014 arXiv:1312.0141 [physics.ins-det]
   
6. 
   Saveliev V. “Silicon avalanche pixel sensor for high precision tracking,” talk at at the 13th Topical Seminar on Innovative Particle and Radiation Detectors (IPRD13), 7-10 October, Siena, Italy
   
7. 
   Saveliev V., SiPM used as PMT devices for ionized particle detection and new trends on related pixel technology, signal processing issues", INFIERI 1st International School on Intelligent Signal Processing for Frontier Research & Industry, 10-16 July 2013, Oxford, England
   

8. 
   M. M. Vignetti, F. Calmon, R. Cellier, P. Pittet, L. Quiquerez, A. Savoy-Navarro, “Design guidelines for the integration of Geiger-mode avalanche diodes in standard CMOS technologies” Elsevier
   
9. 
   Microelectronics Journal, Vol. 46, No 10, pp. 900–910, Oct. 2015 (doi  10.1016/j.mejo.2015.07.002)
   

Posters:

1. 
   Vignetti M., "Development of Novel Pixel Sensors based on 3D CMOS technology for tracking devices", 4th "Intelligent Signal Processing for Frontier Research and Industry” 2nd International Summer School – Universite Paris-Diderot/CNRS, Paris, July 15 to 25, 2014 (publication in JINST Proceedings).
   
2. 
   M.M. Vignetti, M., Calmon F., Cellier R., Pittet P., Quiquerez L., Savoy-Navarro A., "Development of Novel Pixel Sensors based on 3D CMOS technology for tracking devices", 4th "Intelligent Signal Processing for Frontier Research and Industry” (INFIERI) Workshop, NIKHEF-Amsterdam (The Netherlands), December 10-12, 2014
   
3. 
   M. M. Vignetti, et al., Development of Novel Pixel Sensors based on 3D CMOS technology for tracking devices, 3rd INFIERI Summer School, Hamburg, 14-25 September 2015
   

References

V. Saveliev, “Avalanche Pixel Sensor and Related Methods”, US Patent. 8,269,181 (2012)

N. D’Ascenzo, P.S. Marrocchesi, S. Moon, F. Morsani, L.Ratti, V. Saveliev, A. Savoy Navarro and Q. Xie, “Silicon Avalanche Pixel Sensor for High Precision Tracking” 13th Topical Seminar on Innovative Particle and Radiation Detectors IPRD13

Project's co-ordinator: Aurore SAVOY NAVARRO

E-mail: [e-mail]

Period covered: from 01/02/2013 to 31/01/2017
Project website: http://infieri-network.eu