Fast, Interconnected and Efficient devices, for frontier exploitation in R

INtelligent, Fast, Interconnected and Efficient devices, for frontier exploitation in Research and Industry
Funding Scheme: FP7-PEOPLE-2012-ITN
Grant Agreement number: 317446
Project acronym: INFIERI

DELIVERABLE NAME: 3D Very Deep Sub Micron CMOS demonstrator with basic interconnect technology: Design simulation & layout
DELIVERABLE REF. N°: WP2.2
WORK PACKAGE: 2
NATURE OF THE DELIVERABLE: R= Report, P = Prototype, D = Demonstrator, O = Other
BENEFICIARY(IES) CONTRIBUTOR(S): WP2 partners
AUTHOR(S) NAME(S) & EMAIL(S): M. Vignetti as ESR2 ([e-mail]), F. Calmon ([e-mail]), R. Cellier ([e-mail] ) P. Pittet ([e-mail]) , L. Quiquerez ([e-mail]) , A. Savoy-Navarro ([e-mail])
DELIVERY DATE FROM ANNEX 1: M24
DISSEMINATION LEVEL: RE, CO
PU = Public N/A IN THE INFIERI CONTEXT
PP = Restricted to other programme participants (including the Commission Services) N/A IN THE INFIERI CONTEXT
RE = Restricted to a group specified by the consortium (including the Commission Services) HIGHLY SUGGESTED IN THE INFIERI CONTEXT
CO = Confidential, only for members of the consortium (including the Commission Services) HIGHLY SUGGESTED IN THE INFIERI CONTEXT


Abstract

An innovative device based on silicon avalanche structures and exploiting the concept of coincidence detection was proposed as an “Avalanche Pixel Sensor” (APiX): see deliverable WP2.1. The design and layout study was achieved from 2014 to Q2 2015 and a first prototype fabricated in Q3 2015.

Work achieved on:

1. 
   Analysis of the noise count rate in case of coincidence detection
   

The detection of a coincidence event allows discrimination of the signal produced by an incoming ionizing particle from background Ultra-Violet, Visible and Near-Infrared photons and thermal dark counts. Background photons are absorbed by photo-electric effect and detected only by one single avalanche cell, without any coincidence event. Besides dark counts are statistical events due to thermal generated electrons, occurring in each avalanche cell, thus dark counts in one cell are statistically uncorrelated from dark counts in the other cell. A fake coincidence may occur however if a microcell is activated by a thermal generated electron and, within a certain coincidence window, the other cell is activated as well.

As an example of the great benefits provided by the concept of coincidence detection, Figures 1 & 2 show a comparison between the FCR in an APiX and the corresponding dark count rate obtained in traditional avalanche photodiodes in Geiger mode for different coincidence time windows and devices surfaces.

Figure 1: Noise Count Rate for a 50µmX50µm avalanche diode (dotted line) and for 50umX50um APiXs (dotted – dashed lines) as a function of the dark count rate density for several time coincidence windows

Figure 2: Noise Count Rate for an avalanche diode (dotted lines) and for APiXs (dotted – dashed lines) as a function of the dark count rate density for several device surfaces

2. 
   Design guidelines in Geiger mode avalanche diodes realized in standard CMOS technology
   

(this study has been accepted in Elsevier Microelectronics Journal in 2015)

There are several aspects to be carefully accounted for in the design of an avalanche diode operating in Geiger mode, even harder when using a commercial standard CMOS technology with neither control the process parameters nor any detailed information on that. TCAD simulations (Synopsys Sentaurus software), provided useful design guideline at the device level regarding the main challenges to be typically faced in the design of a standard CMOS avalanche diode, more specifically the prevention of premature edge breakdown (PEB) and the minimization of the dark count rate as well as the after-pulsing probability.

Figure 3: Avalanche diode architecture with low doped guard rings

Several diode architectures were studied, and a classical implementation compatible with the CMOS 0,35 µm high-voltage technology from AMS Company (Figure 3) was chosen. This choice is based on (i) Affordable CMOS technology in terms of tape-out costs, (ii) Best performing architecture among those compatible with the chosen CMOS technology. The advantages are: PEB prevented thanks to a low doped p-well guard-ring, expected low Band-to-Band tunneling generation thanks to a low n-type doping in the multiplication region, already used for design of CMOS avalanche diodes showing good DCR levels.

3. 
   Pixel design and associated electronics
   

Based on simulation study, the APiX prototype was designed (see layout [1]).

4. 
   Physical layout
   

Figure 4 illustrates the layout and a photo of the APIX test-chip.

Figure 4: APIX prototype: layout on the left, phots in the middle ad on the right

Related dissemination:

1. 
   Vignetti M., Calmon F., Cellier R., Pittet R., Quiquerez L., Savoy-Navarro A. “A time-integration based quenching circuit for Geiger-mode avalanche diodes” 13th IEEE International New Circuits and Systems Conference (NEWCAS 2015), June 7-10, 2015, Grenoble, France, doi: 10.1109/NEWCAS.2015.7182007
   
2. 
   Vignetti M., Update on the development of Novel Pixel Sensors based on 3D CMOS technology, 6th INFIERI workshop, Pisa, October 27-29 2015
   
3. 
   Vignetti M., Development of Novel Pixel Sensors based on 3D CMOS technology for tracking devices, 5th INFIERI workshop, CERN, April 27-29 2015  
   
4. 
   Vignetti M., "Development of Novel Pixel Sensors based on 3D CMOS technology for tracking devices", 4th "Intelligent Signal Processing for Frontier Research and Industry” (INFIERI) Workshop -  Amsterdam (The Netherlands)  December 10-12, 2014
   
5. 
   Vignetti M., Calmon F. a , Cellier R. a , Pittet P. a , Quiquerez L. a , Savoy-Navarro A., "Development of Novel Pixel Sensors based on 3D CMOS technology for tracking devices",  4th "Intelligent Signal Processing for Frontier Research and Industry” (INFIERI) Workshop -  Amsterdam (The Netherlands)  December 10-12, 2014, (poster) 
   
6. 
   Vignetti M., Calmon F., Cellier R., Pittet P., Quiquerez L. and Savoy-Navarro A., ”Preliminary simulation study of a coincidence avalanche pixel sensor", INFIERI 2nd International School on Intelligent Signal Processing for Frontier Research & Industry, 14-25 July 2014, Paris, France, (poster) in Proceedings published in Journal of Instrumentation, Vol. 10 (C06007), June 2015, doi:10.1088/1748-0221/10/06/C06007
   
7. 
   M. M. Vignetti, F. Calmon, R. Cellier, P. Pittet, L. Quiquerez, A. Savoy-Navarro, “Design guidelines for the integration of Geiger-mode avalanche diodes in standard CMOS technologies” Elsevier Microelectronics Journal, Vol. 46, No 10, pp. 900–910, October 2015 (doi  10.1016/j.mejo.2015.07.002)
   
8. 
   M. M. Vignetti et al., Development of Novel Pixel Sensors based on 3D CMOS technology for tracking devices, 3rd INFIERI Summer School, Hamburg, 14-25 September 2015 (poster)
   

Outreach: “My thesis in 3 minutes” YouTube video: https://www.youtube.com/watch?v=tjOkn8hvcYQ

Project's co-ordinator: Aurore SAVOY NAVARRO

E-mail: [e-mail]

Period covered: from 01/02/2013 to 31/01/2017
Project website: http://infieri-network.eu