peripherals implemented in the Test System are accessed using the OPB.
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.3) On-Chip Memory Controller: An on-chip memory (OCM) interface supports the
attachment of additional memory to the instruction and data caches that can be accessed
at performance levels matching the cache arrays. The On-Chip Memory (OCM)
controller serves as a dedicated interface between the FPGA block RAMs and the OCM
signals contained within the embedded PowerPC 405 core. The data-side OCM
(DSOCM) utilizes the Block RAMs dual-port feature to enable both read and write data
transfer between processor and FPGA. The instruction-side OCM (ISOCM) is used for
the storage of interrupt service routines. The DSOCM was used to write the received
data to the
Logic A nalyzer
Block RAM and then transfer the data to PC for analysis.
In this chapter, the 10 Gigabit Ethernet XAUI system was reviewed. Xilinx Logic cores
that enabled the re-design of 10 Gigabit Ethernet test systems were also reviewed.
Chapter 4 presents the implementation details of the Transmit side of the Test System.
29
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