| 4.2 Future Developments
In future HWICAP (Hardware Internal Configuration Access Port) Logic Core can be
added to the Transmit system. This module enables the PowerPC to read and write to the
FPGA configuration memory through the ICAP (Internal Configuration Access Port).
The user can apply four levels of programmable pre-emphasis values during the circuit
operation to overcome losses and attenuations in the channel. Variable trigger conditions
can also be applied to the built-in Logic Analyzer Module at run time. The Logic
Analyzer module is explained in depth in Chapter 5. Dynamic reconfiguration with out
any glitches cannot be implemented in the design, if the design uses LUTs (Look Up
Tables) or SRL16 (16 bits Serial Shift Register) primitives. The SRL16 has been used in
the design for calculating the word delay. In order to use the HWICAP Logic Core, the
Transmit System has to be redesigned in the future.
38
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.
In this chapter background information about Transmit side of the 10 Gigabit Ethernet
XAUI Test System was presented. Also the various modules of the Transmit test system
were discussed. The 10 Gigabit Ethernet XAUI Receive system architecture and
implementation is presented in Chapter 5.
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39
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