Fpga-based dpwm for Digitally Controlled High-Frequency dc-dc smps



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FPGA-Based DPWM for Digitally Controlled High-Frequency DC-DC SMPS
Gao Yanxia1, Guo Shuibao1, 2, Xu Yanping1, Lin-Shi Xuefang2, Allard Bruno2, IEEE Senior Member
1 School of Mechanical&Electronic Engineering and Automation, Shanghai University, Shanghai, China

E-mail: shuibaoguo@gmail.com, {gaoyanxia, xuyanping }@shu.edu.cn



2 Lab. AMPERE (CNRS UMR 5005)-INSA-Lyon, Villeurbanne Cedex – France

E-mail: {xuefang.shi, bruno.allard}@insa-lyon.fr




Abstract–Digital pulse-width modulator (DPWM) is known as the critical module in digital controller application for high-frequency switching mode power supply (SMPS). This paper presents a new Hybrid DPWM architecture operating at high frequency with high resolution. The proposed DPWM takes advantage of the phase-shift function of Digital Clock Manager (DCM) in FPGA, and combines a counter-comparator with a digital dither block. To verify the proposed DPWM, an 11-bit prototype DPWM is implemented on a FPGA-based digitally controlled high-frequency buck converter. Experimental results with constant switching frequency up to 2MHz validate the functionality of the proposed DPWM. This hybrid architecture can operate at high switching frequency while reduce clock frequency so as to save power consumption.
Keywords–DPWM, DCM phase-shift, digital dither, SMPS, FPGA implementation

I.Introduction

Due to the numerous advantages including advanced control strategy, low sensitivity to variations, simplicity to use digital design tools and re-programmability to different task, digital controller has become an attractive candidate for high-performance switching mode power supply (SMPS) in portable electronic applications [1-2], where the high switching frequency is urgently required so as to reduce passive component size to meet the system miniaturization demand. Fig. 1 shows a diagram block of digitally controlled buck converter.


In spite of so many apparent and potential benefits, some issues still require considering in practical digital control implementation, such as analog-to-digital converter (ADC) sampling delay, quantization error and limited resolution of output voltage, which are focused by many power supply engineers. ADC resolution is becoming a less important issue thanks to windowed ADC techniques [3-5], whereas digital pulse-width modulator (DPWM) brings a trade-off between the clock frequency and the resolution. For example, for an N-bit DPWM at a switching frequency fs, the conventional Counter-Comparator DPWM requires the clock frequency of 2Nfs. When SMPS switches at high frequencies, the high resolution of DPWM will result in very high clock frequency that causes high power consumption and implementation difficulty. Hence, one of the challenges for digitally controlled high-frequency SMPS design is to increase DPWM resolution while keeping the clock frequency low.
Several alternative DPWM solutions which can operate at switching frequencies from hundreds of kHz to 1MHz

Fig. 1: A diagram block of digitally controlled buck converter
have been presented, such as the hardware architectures: Counter-Comparator DPWM [7], Delay-Line DPWM [3], Segmented Delay-Line DPWM [8], Hybrid Delay-Line DPWM [9], Ring-Oscillator DPWM [5], and the soft methods: Digital dither DPWM [6] and Delta-Sigma (Σ-∆) DPWM [10]. Each of them has some advantages and disadvantages. Counter-Comparator DPWM has excellent linearity in the digital-to-time conversion, but a very high clock frequency is needed. Delay-Line, Segmented Delay-Line, Ring-Oscillator DPWM can be seen as similar type structures that use a series of tight logic cells to obtain the fine DPWM resolution while increase chip area. Hybrid Delay-Line DPWM combines the counter-comparator with the delay-line as a compromise between the high clock frequency and the chip area. Digital dither and Σ-∆ DPWM have been proved effective methods to design a high-resolution DPWM in software way without increasing chip area and power consumption. When DPWM comes to implementation in FPGA-based system, two attractive digital techniques, the Delay-Locked Loop (DLL) [11-12] and the segmented DLL [13] have been recently proposed to achieve DPWM. They utilize the DLL phase-shift blocks in FPGA to reduce the clock frequency. In these DPWM applications, the most significant bits (MSBs) of PWM duty value are achieved by the counter-comparator and the least significant bits (LSBs) are realized by the DLL phase-shift block.
Based on the effective software method digital dither [6] and the useful segmented DLL phase-shift technique [13], this paper proposes a Hybrid DPWM, which takes advantage of Digital Clock Manager (DCM) phase-shift in FPGA, and combines a counter-comparator block with a digital dither block. This Hybrid DPWM can get high-resolution DPWM with a reduced clock frequency at high switching frequency. The proposed 11-bit DPWM along with a classical digital PID control law is verified on a FPGA-based digitally controlled buck converter at the switching frequency up to 2MHz.
The proposed DPWM design is described in section II, and its operation procedure is presented in section III. Section IV shows the FPGA-implementation waveforms of the proposed DPWM and illustrates the experimental results of the proposed digital controller verified on a FPGA-based discrete buck converter. The conclusion is given in section V.

II.Proposed 11-bit FPGA-Based Hybrid DPWM

The proposed DPWM includes three blocks: 3-bit digital dither block, 4-bit segmented DCM phase-shift block and 4-bit counter-comparator block. Fig. 2 shows the schematic blocks of the proposed DPWM.



Fig. 2: Proposed DPWM schematic block



1. 3-bit digital dither block


The basic principle of digital dither is detailed in [6]. It consists to distribute the Ndith LSB of the duty ratio in a pre-scheduled sequence and put the specific LSB effects into hardware NDPWM MSB. The (NDPWM + Ndith) bits duty ratio from control law will be modified in an average distribution over 2Ndith switching periods, so that the equivalent duty ratio is in the value between 2Ndith adjacent quantized levels. By digital dither method, the Core DPWM resolution NDPWM can be increased by Ndith bits up to equivalent NDPWM +Ndith bits.
However, dither is not coming free. The longer bits the dither is used, the higher output ripple increases. Thus, this consideration puts a practical limit on the number of dither bits that can be added to increase the resolution of the DPWM. When the digital dither approach is applied to the proposed 11-bit DPWM architecture, the bit number of dither can be determined using those useful mathematical analyses in [6]. The parameters of buck converter are: C=22µF, RESR =10, L=4.7µH, fs =2MHz, NDPWM = 11-bit, NADC = 11-bit, NCore = 8-bit, and Vin =3.3V. According to the determination for the bit number of dither [6], the bit number of dither is limited Ndith <4.8234. Thus, the bit number of dither can be adapted from 1 to 4 in this case. Here, we use a 3-bit digital dither pattern in the 11-bit hybrid DPWM.
In this digital dither approach, the 3-bit digital dither architecture adopts a minimum-ripple dither pattern [6]. Fig. 3 and Fig. 4 show the diagram block of 3-bit digital dither and its minimum-ripple dither scheme respectively. As shown in Fig. 4, where d1 and d2 are two adjacent initial quantized levels with d1 = d2 + LSB. It can be seen that when the duty ratio changes between d1 and d2 in a dither sequence during every 23 switching periods, a corresponding sub-bit level can be implemented by averaging over 8 switching periods. According to Fig. 4, a look-up table is used to store the 23 dither sequences. Each sequence is 23-bit long. Therefore, a 23x23 table is shaped as shown in Table 1 where the 3-bit LSB acts as the line index and the 3-bit counter value performs the row index. The dither value will be added to the d[10:3] by an 8-bit saturated adder, which generates a new duty ratio D[7:0]. As a result, the equivalent resolution of DPWM is increased by 3 bits. For instance, when the 11-bit duty ratio changes from 0.500244 to 0.503664 by 1-bit LSB per switching cycle, the dither results over 23 switching cycles are shown in Table 2, where the small duty ratio error can be eliminated by SMPS filter. The obtained 8-bit value D[7:0] will be sent to the hardware Core DPWM (4-bit segmented DCM phase-shift and the 4-bit counter-comparator) described below.

Fig. 3: A diagram block of 3-bit digital dither


Fig. 4: A 3-bit digital dither minimum-ripple dither scheme


Table 1: 3-bit minimum-ripple dither look-up table


3-bit LSB

3-bit counter (row index)

Sequence

(line index)

0

1

2

3

4

5

6

7

average

000

0

0

0

0

0

0

0

0

0

001

0

0

0

0

0

0

0

1

1/8

010

0

0

0

1

0

0

0

1

2/8

011

0

0

1

0

0

1

0

1

3/8

100

0

1

0

1

0

1

0

1

4/8

101

0

1

0

1

1

0

1

1

5/8

110

0

1

1

1

0

1

1

1

6/8

111

0

1

1

1

1

1

1

1

7/8


2. 4-bit segmented DCM phase-shift block


DCM is available in most FPGA devices. It can implement a clock delay locked loop, a digital frequency synthesizer and digital phase shifter. Here, DCM shifts the clock phase optionally to delay the incoming clock by a fraction of the clock period. For instance shown in Fig. 5, the DCM divides the incoming clock FCLK (50% ratio) into four equal clocks clk_0, clk_90, clk_180 and clk_270 respectively, then the four phase-shifted clocks can act as an equivalent 22FCLK clock with a 4:1 multiplexer. Thus, the clock for the DCM architecture can be reduced by 22 times for a fixed-resolution, or the resolution can be increased by 2 bits for a fixed frequency. Since the relationship between system clock FCLK, hardware DPWM resolution NDPWM and switching frequency fs, can be written as (1):
(1)

Table 2: State signals of 3-bit dither schema and duty ratio value over 23 switching cycles

counter

duty value d[10:0]

desired duty ratio

dither value

actual duty value D[7:0]

actual duty ratio

duty ratio error

0

10000000000

0.500244

0

10000000

0.501961

0.1717%

1

10000000001

0.500733

1

10000001

0.505882

0.5149%

2

10000000010

0.501221

1

10000001

0.505882

0.4661%

3

10000000011

0.501710

1

10000001

0.505882

0.4172%

4

10000000100

0.502198

1

10000001

0.505882

0.3684%

5

10000000101

0.502687

1

10000000

0.505882

0.3195%

6

10000000110

0.503175

1

10000001

0.505882

0.2707%

7

10000000111

0.503664

1

10000001

0.505882

0.2218%


Fig. 5: DCM four-phase-shift scheme
Then the required clock FDCM for the four-phase-shift DCM module can be expressed as:
(2)
where NDCM is the bit number of DPWM implemented by four-phase-shift DCM module.
A segmented DCM phase-shift architecture which uses two DCM phase-shift modules in series for digital clock application was introduced in [13]. This segmented DCM architecture is also employed as a 4-bit DPWM block of high-frequency digital control in this paper. Because the proposed DPWM includes a 4-bit counter comparator, the hardware clock frequency is FCLK =24fs. According to (2), the clock frequency FDCM for the segmented DCM module, FDCM = FCLK ∙2 (4-2) = 26fs. The diagram block of the 4-bit segmented DCM phase-shift architecture is shown in Fig. 6, where the input clock FCLK, propagates in zero delay through the first DCM block, DCM-I in this case, and the first phase shifted versions, PX0, PX 90, PX 180 and PX 270, are generated. The clock FDCM, four times as high as the incoming clock FCLK, is operated at the second DCM block, DCM-II, and further phase shifted signals of the clock are produced, PY0, PY90, PY180 and PY270. As observed from Fig. 6, the resolution is now increased by 16 times without increasing the whole system clock frequency by 16 times.

Fig. 6: A diagram block of 4-bit segmented DCM phase-shift

Using two multiplexers to select the corresponding shifted clock signals, the whole block realizes D[3:0], which is the 4 LSBs of DPWM duty D[7:0] from digital dither block. Depending on duty ratio D[3:2], S1 can be derived from the four phase-shifted clock signals PX0, PX 90, PX 180 and PX 270. The selected S1 acts as an equivalent clock of four times (x4) the phase-shifted signals. Similarly, duty ratio D[1:0] selects one of the four phase-shifted clock signals PY0, PY90, PY180 and PY270 for S2 which acts an equivalent clock of four times (x4) the phase-shifted signals. Then the two selected signals are operated in logic AND circuit to generate the final phase-shift signal SC which is 16 times (double x4) as high as the incoming clock FCLK and will be sent to counter comparator. The most attractive merit for this segmented DCM phase-shift architecture is that the final output signal Sc has 24 kinds of clock possibilities during each of FCLK clock cycle, where S1 has 22 kinds of “coarse” phase-shift and S2 has 22 kinds of “fine” phase-shift. Thus, this segmented DCM block can either increase 4-bit DPWM resolution (for fixed fs) or increase the switching frequency by 24 times (for fixed NDPWM). The operation waveforms of the 4-bit segmented DCM phase-shift module are shown in Fig. 7.



Fig. 7: Operation waveforms of the 4-bit segmented DCM phase-shift

3. 4-bit counter-comparator block


Counter-comparator is one simple method to achieve digital-to-time conversion in DPWM. This architecture uses a cycling counter and a comparator, setting a set-reset (SR) latch high when the counter value is zero and low when the counter reaches the control duty ratio d. This scheme has the advantage of a simple structure and an excellent linearity in the digital-to-time conversion. According to (1), it needs 2Nfs clock to achieve an N-bit DPWM at switching frequency fs. However, when it operates at the high frequency fs, it falls into the drawback of very high power consumption. Thus, the counter-comparator is generally used as the solution for few-bit MSBs inside DPWM architectures.
Linking to the digital dither block and segmented DCM phase-shift block above, a 4-bit counter-comparator block shown in Fig. 8 is used here. It includes a 4-bit counter, a 4-bit comparator and a FDP (D Flip-Flop with Asynchronous Preset). D[7:4] and SC respectively come from previous digital dither block and segmented DCM phase-shift block. For example, when D[7:4]=”1010” and D[3:0]=”1011”, the operation waveforms of this 4-bit counter comparator block are shown in Fig. 9.

Fig. 8: 4-bit counter-comparator block linked to digital dither block and segmented DCM block

Fig. 9: Operation waveforms of the 4-bit counter-comparator



III.Operation of the Proposed DPWM Scheme

Taking a combination of three blocks described above: digital dither block, DCM phase-shift block and counter comparator, the completed DPWM architecture can be figured in Fig. 10.


In the FPGA implementation, the 11-bit DPWM signal with 2MHz switching frequency is realized by the proposed Hybrid DPWM architecture. Among the 11-bit DPWM, 3-bit are implemented by digital dither (Ndith=3), 4-bit are achieved by segmented DCM phase-shift block (NDCM = 4), and 4-bit are generated by counter-comparator (NDPWM = 4). According to (1) and (2), respectively, the system external clock is FCLK = 24fs and the clock inside FPGA is FDCM = 22FCLK = 26fs. With the switching frequency of fs = 2MHz, FCLK is merely 32MHz and FDCM is 128MHz while under the same condition the FCLK will be required 29 MHz, 210 MHz and 28 MHz by methods of digital dither [6], DLL phase-shift [11] and segmented DCM phase-shift [13] respectively. Hence, the proposed DPWM can dramatically alleviate the clock requirement at high switching frequency to achieve low power consumption.
An example is employed to explain the operation procedure: Supposing that the duty ratio from the control algorithm is d[01010101010] and the 3-bit counter value in digital dither block is “010”. According to Table 1, when the 1-bit dither value is ‘1’, which will be added to d[10:4] by a saturated adder resulting in a new duty D[01010110]. The D[7:4] = ”0101” is implemented by the 4-bit counter-comparator, D[3:2]=”01” is used to select phase-shifted clock PX90 for S1, and D[1:0] = ”10” is set to select phase-shifted clock PY180 for S2. Through the logic AND operation of S1 and S2, the final phase-shifted signal Sc is obtained and sent to FDP to change PWM signal. The waveforms of the example operation are shown in Fig. 11.

IV.Implementation of a FPGA-Based Digitally Controlled Buck Converter

The implementation of the proposed 11-bit Hybrid DPWM is performed on the Xilinx Virtex-II Pro XC2VP30 FPGA. It has 8 DCM modules and high speed of signal process capability (up to 400MHz inside FPGA and 200MHz for interface I/Os signal transfer). The proposed 11-bit DPWM operating at fs=2MHz requires clock FCLK =32MHz (FDCM =128MHz inside DCM). Compared with the maximum speed of signal process, FDCM and FCLK in this DPWM are very low.


Fig. 12 and Fig. 13 are the simulations results of DCM phase-shift block.
Finally, the simulation for the complete 11-bit proposed FPGA-based DPWM is shown in Fig. 14, which has a duty ratio D[7:0]=”10000011”.
To experimentally verify the proposed DPWM in digitally controlled SMPS, a discrete buck converter with 3.0V input and 1.5V output voltage is fabricated. The filter elements of buck converter are: L = 4.7µH, C = 22µF, load R = 5Ω, and a classical PID control algorithm [14] is employed to regulate the output voltage. The closed-loop dynamics is set to a classical second-order system with a resonant frequency ω of 20 times the open-loop pulsation, and a damping ratio is set ζ = 0.7. External clock fCLK = 32MHz is used on the Virtex-II Pro XC2VP30 board. The voltage feedback is performed by a 10-bit A/D converter AD9203. The diagram block for the digitally controlled buck converter system is shown in Fig. 15. The parameters of the digital controller are given in Table 3.

Fig. 10: Proposed 11-bit FPGA-based DPWM with 3-bit digital dither block, 4-bit segmented DCM phase-shift block and 4-bit counter-comparator block


Fig. 11: Waveforms of example operation in proposed 11-bit DPWM








Fig. 12: DCM four-phase-shift simulation waveforms


Fig. 13: 4-bit segmented DCM phase-shift simulation waveforms




Fig. 14: 11-bit proposed DPWM simulation waveforms




Table 3: Parameters of the digital controller

Buck

Switching power converter

Step down

PID

Digital control algorithm

linear control

fs

Switching frequency

2MHz

ADC

AD9203

10-bit

DPWM

Proposed hybrid DWPM

11-bit

NDPWM

Counter comparator resolution

4-bit

Ndith

Digital dither resolution

3-bit

NDCM

DCM phase-shift resolution

4-bit

FCLK

DPWM counter frequency

32MHz


Fig. 15: Diagram block of digitally controlled buck converter
Fig. 16 shows the PWM signal and output voltage waveforms when the proposed DPWM operates at 2MHz in open-loop with duty ratio 50%.
The proposed DPWM is also applied with the PID control law. When it operates in steady-state, the output voltage and the high-side PWM signal (Pmos) is shown in Fig. 17. When the load R varies from 0.3A to 0.5A (i.e. R from 5Ω to 3Ω), the output voltage transient response is figured in Fig. 18, and the dynamic PWM signal is shown in Fig. 19. From the view of spectrums of PWM gate signals and voltage, the performance of Hybrid DPWM is quite satisfying. Although the PID control does not offer a high dynamic performance (i.e. the duty ratio d is not optimal), the proposed DPWM faithfully address the digital-to-time conversion in dynamic state (shown in Fig. 19). Other advanced control scheme with better performances can be used in the digital controller. Whatever the paper addresses specifically the implementation and the performances of the DPWM block required with any digital controller.

Fig. 16: DPWM operating at 2MHz in open-loop with duty 50%


Fig. 17: High-side PWM signal and output voltage in steady-state with PID control


Fig. 18: Output voltage dynamic response when the load varies from 5Ω to 3Ω (the load current from 0.3A to 0.5A) in PID control


Fig. 19: PWM signal in dynamic state with PID control



V.Conclusion

This paper presents a fully synthesizable 11-bit Hybrid DPWM combined of a 4-bit DCM phase-shift block, a 4-bit counter-comparator block and a 3-bit digital dither block. The most attractive advantage of the proposed DPWM is the fully synthesizable DCM resource available in most FPGA devices, which makes the proposed DPWM particularly suitable for FPGA-based digital controllers in high frequency application. Instead of 211fs, the proposed 11-bit DPWM architecture only requires 24fs clock to implement, which dramatically reduces the power consumption. Based on a Xilinx Virtex-II Pro FPGA board, the proposed DPWM along with a digital PID control law has been experimentally verified on a discrete buck converter operating up to 2MHz.



Acknowledgement


This paper and its related research are partly supported by grants from Power Electronics Science Education Development Program of Delta Environmental & Education Foundation (Project No.DERO2007014). The authors would like to explain acknowledgement for the plan.


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