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5.6.2Contributions5.6.2.1.1.1.1.1.1JCTVC-F151 CE6 Subtest A: Cross-check report on Bidirectional UDI mode (JCTVC-F509) [H. L. Tan, Y. H. Tan, C. Yeo (I2R)] 5.6.2.1.1.1.1.1.2JCTVC-F204 CE6.a: Cross-check of cases 7 and 8 for BUDI [X. Peng (USTC), J. Xu (Microsoft)] 5.6.2.1.1.1.1.1.3JCTVC-F348 Cross-check report on CE6.a BUDI [Keiichi Chono, Hirofumi Aoki (NEC)] 5.6.2.1.1.1.1.1.4JCTVC-F509 CE6.a: Report of Bidirectional UDI mode for Intra prediction [Y. Lin (HiSilicon), H. Yang (Huawei), C. Lai (HiSilicon), J. Zheng (HiSilicon), L. Liu (HiSilicon)] 5.6.2.1.1.1.1.1.5JCTVC-F565 CE6.a: Cross Check of Tests 9 and 10 for BUDI Mode (JCTVC-F509) [G. Van der Auwera (Qualcomm)] 5.6.2.1.1.1.1.1.6JCTVC-F110 CE6.b Test 4: LM mode harmonization on SDIP [J. Lim, B. Jeon (LGE)] 5.6.2.1.1.1.1.1.7JCTVC-F139 CE6.b: Cross-check of Test 2 Case 1 (Huawei JCTVC-F506) [J. Jung, J. Le Tanou (Orange Labs)] 5.6.2.1.1.1.1.1.8JCTVC-F155 CE6 Subtest B: Cross-check report on SDIP Test 2b (JCTVC-F506) [C. Yeo, Y. H. Tan (I2R)] 5.6.2.1.1.1.1.1.9JCTVC-F195 CE6.b Test 4: Cross-verification results of Microsoft's LM mode harmonization on SDIP (JCTVC-F196) by LG [J. Lim, B. Jeon (LGE)] 5.6.2.1.1.1.1.1.10JCTVC-F196 CE6.b Report of Test 4: Harmonization of LM mode and the chroma prediction in SDIP [X. Peng (USTC), J. Xu (Microsoft)] 5.6.2.1.1.1.1.1.11JCTVC-F197 CE6.b Report of Test 3: Interaction between SDIP and MDCS [X. Peng (USTC), J. Xu (Microsoft)] 5.6.2.1.1.1.1.1.12JCTVC-F231 CE6.b: Cross-check report of Test 3 : Interaction between SDIP and MDCS, proposal JCTVC-F197 [R. Boitard, L. Guillo (INRIA)] 5.6.2.1.1.1.1.1.13JCTVC-F239 CE6.b: Crosscheck of SDIP+Mode dependent DCT/DST (test2, case3) (JCTVC-F506) [M. Budagavi (TI)] 5.6.2.1.1.1.1.1.14JCTVC-F308 CE6.b Cross-check of Test1: Interaction between SDIP and RQT [J. Xu, A. Tabatabai (Sony)] 5.6.2.1.1.1.1.1.15JCTVC-F309 CE6.b Cross-check of Test3: Interaction between SDIP and MDCS [J. Xu, A. Tabatabai (Sony)] 5.6.2.1.1.1.1.1.16JCTVC-F336 CE6.b.5 Report: Harmonization of SDIP and MDIS [G. Li, N. Ling (Santa Clara Univ.), L. Liu, C. Lai, J. Zheng, P. Zhang (Hisilicon)] 5.6.2.1.1.1.1.1.17JCTVC-F349 Cross-check report on CE6.b SDIP [K. Chono, H. Aoki (NEC)] 5.6.2.1.1.1.1.1.18JCTVC-F392 CE6.b: Cross-check of Short Distance Intra Prediction (SDIP) [T. Yamamoto (Sharp)] 5.6.2.1.1.1.1.1.19JCTVC-F437 CE6.b: Crosscheck Report of Qualcomm's Proposal JCTVC-F556 [M. Guo, X. Guo (MediaTek)] 5.6.2.1.1.1.1.1.20JCTVC-F489 CE6.b test6 : cross-checking of results from Huawei/Hisilicon on SDIP+Planar [Edouard François (Canon)] 5.6.2.1.1.1.1.1.21JCTVC-F506 CE6.b: Harmonization of SDIP and MDDT [H. Yang, J. Zhou, H. Yu, C. Lai (Huawei)] 5.6.2.1.1.1.1.1.22JCTVC-F518 CE6.b Test6: Report of harmonization on Planar prediction in SDIP [Y. Lin, C. Lai (HiSilicon), X. Cao (Tsinghua), J. Zheng, L. Liu (HiSilicon)] 5.6.2.1.1.1.1.1.23JCTVC-F532 CE6.b Test Summary and spec text of SDIP [X. Cao, Y. Wang, Y. He(Tsinghua), X. Peng(USTC), G. Li(Santa Clara University), J. Xu(Microsoft), H. Yang, H. Yu(Huawei), C. Lai, Y. Lin, L. Liu, J. Zheng(HiSilicon)] 5.6.2.1.1.1.1.1.24JCTVC-F533 CE6.b Report on test1 Harmonization of SDIP and RQT [X. Cao, Y. Wang, Y. He(Tsinghua), X. Peng(USTC), J. Xu(Microsoft), H. Yang, H. Yu(Huawei), C. Lai, Y. Lin, L. Liu, J. Zheng(HiSilicon)] 5.6.2.1.1.1.1.1.25JCTVC-F536 CE6.b Report on test7 Harmonization of SDIP and deblocking filter [X. Cao, Y. He(Tsinghua), X. Peng(USTC), J. Xu, F. Wu(Microsoft), C. Lai, J. Zheng(HiSilicon), H. Yu(Huawei)] 5.6.2.1.1.1.1.1.26JCTVC-F539 CE6.b Test8 Crosscheck report for Qualcomm's results [C. Lai, L. Liu, J. Zheng(HiSilicon)] [late upload 07-10] 5.6.2.1.1.1.1.1.27JCTVC-F556 CE6.b: Report on SDIP Harmonization with Deblocking, MDIS, MDCS, and HE Residual Coding [G. Van der Auwera, J. Sole, Y. Zheng, X. Wang, I. S. Chong, R. Joshi, M. Karczewicz (Qualcomm)] 5.6.2.1.1.1.1.1.28JCTVC-F638 CE6.b: Cross-verification of Qualcomm’s JCTVC-F556 section 4 on SDIP Harmonization for HE Residual Coding [V. Seregin, J. Chen (Samsung)] [late reg. 07-05, upload 07-06] 5.6.2.1.1.1.1.1.29JCTVC-F674 Cross Check of CE6.b Test 5 (JCTVC-F556) on SDIP Harmonization with MDIS [J. Zhao, A. Segall (Sharp)] [late reg. 07-07, upload 07-07] 5.6.2.1.1.1.1.1.30JCTVC-F557 CE6.b SDIP Harmonization: Cross Check Results for Test 5 on MDIS and Test 7 on Deblocking (JCTVC-F532) [G. Van der Auwera (Qualcomm)] 5.6.2.1.1.1.1.1.31JCTVC-F630 CE6.b4:Cross-check results (JCTVC-F026) [A. Gabriellini, M. Mrak (BBC)] [late reg. 07-04, upload 07-04] 5.6.2.1.1.1.1.1.32JCTVC-F684 CE6.b: Additional simulation results of RQT and SDIP harmonization [Keiichi Chono (NEC), Krit Panusopone (Motorola Mobility)] [late reg. 07-07, upload 07-07] 5.6.2.1.1.1.1.1.33JCTVC-F697 Crosscheck for additional simulation results of RQT and SDIP harmonization from NEC and Motorola Mobility (JCTVC-F684) [C. Lai, L. Liu, J. Zheng (HiSilicon)] [late reg. 07-10, upload 07-10] 5.6.2.1.1.1.1.1.34JCTVC-F566 CE6.c: Differential Coding of Intra Modes [Ehsan Maani, Tomoyuki Yamamoto, Akiyuki Tanizawa, Taichiro Shiodera, Virginie Drugeon] This document presents the description and results of Differential Coding of Intra Modes (DCIM) of JCTVC-B109. On average, using this technique, 0.8% and 0.7% gain is achieved compared to HM 3.0 anchors for High Efficiency (HE) and Low Complexity (LC) settings, respectively. The presentation deck provides additional results combining SDIP and DCIM, showing that gain of 0.4% is retained (not in Word file). Decoding time increases by roughly 3% for HE, 5-6% for LC. Four different versions were presented which are different in terms of encoding time increase 6–13% for HE, 14–24% for LC, 0.4–0.8% for HE, 0.1–0.7% for LC. Question: What are worst-case numbers for decoding time increase? Could be up to 30%. Comment: Gain in terms of BR reduction is only half of what was reported last time, whereas the encoding time went up. This seems to be a general tendency of all intra coding methods currently investigated. Conclusion: In terms of tradeoff gain vs. complexity, this should not be adopted. Further study (there may be similar approaches suggested in the non-CE category). 5.6.2.1.1.1.1.1.35JCTVC-F240 CE6.c: Crosscheck of DCIM (case 4) (JCTVC-F566) [M. Budagavi (TI)]
This contribution reports results for the parallel intra prediction concept that was proposed in JCTVC-E315. The parallel prediction unit (PPU) defines a group of pixels that are intra-coded in a parallel fashion. Parallelization is achieved by partitioning the intra-coded blocks into two sets. Blocks in the first set are predicted in parallel using available pixels outside the PPU; blocks in the second set are also predicted in parallel using available pixels outside the PPU as well as pixels from the first set of blocks. Here, the performance of the parallel intra prediction is reported in the context of HM3.0. Three configurations are considered. First, a “checkerboard” partitioning is considered. Second, a “stripe” configuration is reported. Finally, for comparison, the impact of disabling 4x4 prediction completely (but allowing 4x4 transforms) is reported. For the case of parallel intra prediction with stripe partitioning, an average coding efficiency impact of 0.2%, 0.5% and 1.3% for, respectively, low delay, random access, and all intra common test conditions was reported. For the case of checker board partition, there is a coding efficiency impact of 1.5% and 1.8% for all intra and intra LC coding. In comparison, disabling 4x4 prediction (8x8 prediction with 4x4 residuals) results in 3.9% and 5.3% rate increase for intra and intra LC configurations. Main question to be clarified: Is parallelism at the level of PUs needed? Comparison against parallelism at slice level? Slice-level parallelism may be the better way to go. No support was expressed to adopt this. No request was made for further information, such that the results of this CE could be referred to in the future when potentially more evidence might be available that this kind of parallelism is needed. 5.6.2.1.1.1.1.1.40JCTVC-F583 CE6.d: Cross Check Result for Sharp’s Parallel Intra Coding (JCTVC-F605) [G. Van der Auwera (Qualcomm)] 5.6.2.1.1.1.1.1.41JCTVC-F628 CE6.d: Cross Check Result for Sharp’s Parallel Intra Coding (JCTVC-F605) by ETRI [Seunghyun Cho, Sukho Lee, Nakwoong Eum (ETRI)] [late reg. 07-04, upload 07-04] 5.6.2.1.1.1.1.1.42JCTVC-F126 CE6.e: Report on Mode-Dependent Intra Smoothing Modifications [G. Van der Auwera, X. Wang, M. Karczewicz (Qualcomm)] This contribution proposes modifications to mode-dependent intra smoothing (MDIS), which is studied in CE6.e. The decision mapping table is updated and planar mode is included. On average the BD-rate impact is −0.1% for both intra-coding test conditions, while execution times are unchanged. For the BasketballDrill (class C) sequence, the coding impacts are −0.9% (HE) and −1.8% (LC). It was proposed to adopt the MDIS modifications into the HM. Note: As before, the table is trained from a large set of sequences including our test set. It was, however, commented by several experts (including the cross-verifiers) that the new table is more consistent (symmetry of modes, etc.). Decision: Adopt the new LUT as suggested in JCTVC-F126. 5.6.2.1.1.1.1.1.43JCTVC-F171 CE6.e: Cross-verification report on Qualcomm’s improved MDIS (JCTVC-F126) [A. Minezawa, K. Sugimoto, S. Sekiguchi (Mitsubishi)]
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