MicroWind manual



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National Institute of Applied Sciences

Department of Electrical & Computer Engineering





Version 1.0

Etienne Sicard


Unpacking
Your package for MICROWIND contains the following items:
u The User's Manual (the present book)

u The diskettes containing the software, running in Windows 95 environment


The User's manual contains information on how to operate the program and how to execute the commands. It also contains explanations for a set of 30 micro-electronics projects and suggested activities.
System Requirements
Your computer system should have a PC configuration including the following features:
l A minimum memory of 8 Mb

l 640x480, 256 colors (a 800x600 resolution is recommended)

l Windows 95/NT
How to Install the Software
The installation of the software on the hard-disk is recommended. To install the programs on the hard-disk, perform the following step-by-step procedure:
ΠSelect Start -> Execute command under Windows 95,

 Insert the diskette into drive a:

Ž Type a :install and press ¿

This command creates a directory named « microwind » on the hard-disk.

Consequently all the files of the diskette will be copied into this

« microwind » directory.



About the Single License
The single license authorizes you to use one copy of the software and includes one copy of the documentation. You may use the copy of the software and the documentation on no more than one personal computer at a time. You are allowed to make one archival copy of the software for your personal use. You may not transfer, sell, or distribute the software. You cannot give copies of the software or of the documentation to anyone.
ISBN 2-87649-017-X

Edited by INSA Toulouse, Av de Rangueil 31077 Toulouse Cedex 4 - FRANCE


About the Site License
The site license authorizes you to use ten copies of the software and includes one copy of the documentation. For each computer when operating the program simultaneously one more than one computer an authorized copy of the program is required for each of them You can make archival copies of the software. You may not transfer, sell, or distribute the software. You cannot give copies of the software or the documentation to any person.

About the author
ETIENNE SICARD was born in Paris, France, in June 1961. He received a B.S degree in 1984 and a PhD in Electrical Engineering in 1987 both from the University of Toulouse. He was granted a Monbusho scholarship and stayed 18 months at the University of Osaka, Japan. Previously a professor of electronics in the department of physics, at the University of Balearic Islands, Spain, E. Sicard is currently an associate professor at the INSA Electronic Engineering School of Toulouse. His research interests include several aspects of CAD tools for the design of integrated circuits including crosstalk fault analysis, electromagnetic compatibility, the design of micro-systems and of educational software.
Copyright © 1998

Etienne Sicard

INSA-DGEI Av de Rangueil

31077 TOULOUSE Cedex 4, FRANCE

Tel : +33.561.55.98.42

Fax: +33.561.55.98.00

e-mail: etienne@dge.insa-tlse.fr

web information : http ://www.insa-tlse.fr/~etienne


o Windows 95 is a trade mark of MICROSOFT CORPORATION.

o IBM PC is a trademark of INTERNATIONAL BUSINESS MACHINE CORP.



Contents
Page

Software Installation 2

Introduction 6

License 7

1. Tutorial on MOS devices 8

The Mos Model 1 15

The MOS Model 3 16

Tutorial on Level 3 Parameters 18

2. Design of a CMOS Inverter 22

Simulation 27

Parametric Analysis 31

3. Basic Gates 34

Compiling the NAND Gate 35

3-Input OR 37

The XOR gate 39

Complex Gates 41

4. Arithmetic Gates 43

Half-Adder 43

Full Adder 46

Comparator 48

5. Latches & Memories 50

RS Latch 50

D Latch 52

RAM Memory 54

RAM 4x4 bit 56

Contents (ctd)
6. Other Projects 62

4 Bit Adder 62

Multiplier 2x2 bits 64

Two-Bit Counter 66

Wide Range Amplifier 68

Interface with PSPICE 70

Analog/Digital Converter 71

Digital/Analog converter 74

Input/Output Pad, 76

Pad Ring 78

7. Design Rules 82

8. Program Operation 92

9. List of Commands 93

10. Quick Reference Sheet 116

11. Instructor's Guide 121

12. References 123




Introduction

The present book is a guide to using the « Microwind » educational software on a PC computer.


The MICROWIND program allows the student to design and simulate an integrated circuit. The package itself contains a library of common logic and analog ICs to view and simulate. MICROWIND includes all the commands for a mask editor as well as new original tools never gathered before in a single module. You can gain access to Circuit Simulation by pressing one single key. The electric extraction of your circuit is automatically performed and the analog simulator produces voltage and current curves immediately.
A specific command displays the characteristics of pMOS and nMOS, where the size of the device and the process parameters can be very easily changed. Altering the MOS model parameters and, then, seeing the effects on the Vds and Ids curves constitutes a good interactive tutorial on devices.
The Process Simulator shows the layout in a vertical perspective, as when fabrication has been completed. This feature is a significant aid to supplement the descriptions of fabrication found in most textbooks.
The Logic Cell Compiler is a particularly sophisticated tool enabling the automatic design of a CMOS circuit corresponding to your logic description in VERILOG. The DSCH software, which is a user-friendly schematic editor and a logic simulator presented in a companion manual, is used to generate this Verilog description. The cell is created in compliance with the environment, design rules and fabrication specifications.
A set of CMOS processes ranging from 1.2µm down to state-of-the-art 0.25µm are proposed.

The chapters of this manual have been summarized below. Chapters One through Six present a tutorial on micro-electronics and IC design. Chapter One is dedicated to the simulation of the single MOS device, with details on the device modelling. Chapter Two presents the CMOS Inverter, Chapter Three the basic logic gates, Chapter Four the arithmetic functions. The latches and memories are detailed in Chapter Five. As for Chapter, it deals with various projects such as a counter, a multiplier, a CMOS analog amplifier, the Analog/Digital and Digital/Analog converter principles and a RAM memory.


The detailed explanation of the design rules is in Chapter Seven. The program operation and the details of all commands are given in Chapter Eight and Nine. A Quick reference sheet, the complete list of files and the instructor guide are reported at the end of the present manual.
The major updates of MICROWIND compared to the DOS version concern the support of advanced technologies, improvements in editing commands, the possibility to handle very complex designs and the VERILOG compilation from high-level description into layout. The new software, DSCH, concerning logic editing and simulation is now part of the package.
License
Please note that MICROWIND is a licensed software, that has been licensed in France by Langage et Informatique Inc, Toulouse, and by INSA in all other countries.
The single license authorizes you to use one copy of the software and includes one copy of the documentation. The site license authorizes you to use ten copies of the software and includes one copy of the documentation. An authorized copy of the program is required for each one of the computer operating the program simultaneously. You may not transfer, sell, or distribute the software.
MICROWIND is recommended by EURO-PRACTICE, the American Society for Engineering Education (ASEE), and supported by the National Comity for Micro-Electronics Education (CNFM).

1. Tutorial on MOS Devices
To use the MICROWIND program use the following procedure:
ΠGo to the directory in which the software has been copied

(The default directory is MICROWIND)


 Double-click on the MicroWind icon
The MICROWIND display window is shown in Figure 1. It includes four main windows: the main menu, the layout display window, the icon menu and the layer palette. The cursor appears in the middle of the layout window and is controlled by using the mouse.
The layout window features a grid that represents the current scale of the drawing, scaled in lambda (l) units and in micron.
The lambda unit is fixed to half of the minimum available lithography of the technology. The default technology is a 0.8 µm technology, consequently lambda is 0.4 µm.


Fig. 1. The MICROWIND window as it appears at the initialization stage..

The MOS device
The MOS symbols are reported below. The n-channel MOS is built using polysilicon as the gate material and N+ diffusion to build the source and drain. The p-channel MOS is built using polysilicon as the gate material and P+ diffusion to build the source and drain.


Manual Design

By using the following procedure, you can create a manual design of the n-channel MOS. The default icon is the drawing icon shown above. It permits box editing. The display window is empty. The palette is located in the lower right corner of the screen. A red color indicates the current layer. Initially the selected layer in the palette is polysilicon. The two first steps are illustrated in Figure 2.


ΠFix the first corner of the box with the mouse.

 While keeping the mouse button pressed, move the mouse to the

opposite corner of the box.

Ž Release the button. This creates a box in polysilicon layer as shown in Figure 2.

The box width should not be inferior to 2 l, which is the minimum width of the

polysilicon box.





Fig. 2. Creating a polysilicon box.
Change the current layer into N+ diffusion by a click on the palette of the Diffusion N+ button. Make sure that the red layer is now the N+ Diffusion. Draw a n-diffusion box at the bottom of the drawing as in Figure 3. N-diffusion boxes are represented in green. The intersection between diffusion and polysilicon creates the channel of the nMOS device.


Fig. 3. Creating the N-channel MOS transistor

Process Simulation

Click on this icon to access process simulation. The cross-section is given by a click of the mouse at the first point and the release of the mouse at the second point. In the example below (Figure 4), three nodes appear in the cross-section of the n-channel MOS device: the gate (red), the left diffusion called source (green) and the right diffusion called drain (green), over a substrate (gray). The gate is isolated by a thin oxide called the gate oxide. Various steps of oxidation have lead to a thick oxide on the top of the gate.




Fig. 4. The cross-section of the nMOS devices.
The physical properties of the source and of the drain are exactly the same. Theoretically, the source is the origin of channel impurities. In the case of this nMOS device, the channel impurities are the electrons. Therefore, the source is the diffusion area with the lowest voltage.
The polysilicon gate floats over the channel, and splits the diffusion into 2 zones, the source and the drain. The gate controls the current flow from the drain to the source, both ways. A high voltage on the gate attracts electrons below the gate, creates an electron channel and enables current to flow. A low voltage disables the channel.
Mos Characteristics

Click on the MOS characteristics icon. The screen shown in Figure 5 appears. It represents the Id/Vd simulation of the nMOS device.


Fig. 5. N-Channel MOS characteristics.
The MOS size (width and length of the channel situated at the intersection of the polysilicon gate and the diffusion) has a strong influence on the value of the current. In Figure 5, the MOS width is 12.8µm and the length is 1.2µm. Click on OK to return to the editor. A high gate voltage (Vg =5.0) corresponds to the highest Id/Vd curve. For Vg=0, no current flows. The maximum current is obtained for Vg=5.0V, Vd=5.0V, with Vs=0.0.
The MOS parameters correspond to SPICE Level 3. You can alter the value of the parameters, or even access to Level 1. You may also skip to PMOS. You may as well add some measurements to fit the simulation. Finally, you can simulate devices with other sizes in the proposed list.
Add Properties for Simulation
Properties must be added to the layout to activate the MOS device. The most convenient way to operate the MOS is to apply a clock to the gate, another to the source and to observe the drain. The summary of available properties is reported below.

 Apply a clock to the drain. Click on the Clock icon, click on the left diffusion. The Clock menu appears (See below). Change the name into « drain » and click on OK. A default clock with 3 ns period is generated. The Clock property is sent to the node and appears at the right hand side of the desired location with the name « drain ».



Fig. 6. The clock menu.
 Apply a clock to the gate. Click on the Clock icon and then, click on

the polysilicon gate. The clock menu appears again.

Change the name into « gate» and click on OK to apply a clock with 6 ns period.
 Watch the output: Click on the Visible icon and then, click on the right diffusion.

The window below appears. Click OK. The Visible property is then sent

to the node. The associated text « s1 » is in italic. The wave form of this node

will appear at the next simulation.




Fig. 7. The visible node menu.

Save before Simulation
Click on File in the main menu. Move the cursor to Save as ... and click on it. A new window appears, into which you enter the design name. Type, for example, myMos. Use the keyboard for this and press ¿. Then click on OK. After a confirmation question, the design is saved under that filename.
IMPORTANT : Always save BEFORE any simulation !
Analog Simulation

Click on Simulate on the main menu. The timing diagrams of the inverter appear, as shown in Figure 8.



Fig. 8. Analog simulation of the MOS device.
When the gate is at zero, no channel exists so the node s1 is disconnected from the drain. When the gate is on, the source copies the drain. It can be observed that the nMOS device drives well at zero but at the high voltage. The final value is 4.2V, that is VDD minus the threshold voltage. Click on More in order to perform more simulations. Click on Stop to return to the editor.

The MOS Model 1
For the evaluation of the current Ids between the drain and the source as a function of Vd,Vg and Vs, you may use the old but nevertheless simple MODEL 1 described below. The model 1 is accurate for channel length of more than 10µm.
CUT-OFF MODE. Vgs<0

Ids = 0


LINEAR MODE. VdsIds = KP ((Vgs-Vt)Vds- ))
SATURATED MODE. Vds>Vgs-Vt,
Ids = KP/2 (Vgs-Vt)2

In those formulas, W is the MOS channel width, L is the MOS channel length. VTO is the threshold voltage. The parameter KP is evaluated by the following formula: µn is the mobility of electrons, µp the mobility of holes, and TOX the gate oxide thickness.


KP(n) = µn e0 eS / TOX

KP(p) = µp e0 eS / TOX


where (0.8µm technology)
µn = 510 V.cm-2 µp = 270 V.cm-2

er (SiO2)= 3.9 e0 = 8.85 e -14 Farad/cm

TOX = 150 nm

When dealing with sub-micron technology, the model 1 is 200-300% higher than the measurements, as shown above for the prediction of a 20x0.8µm n-channel MOS with KP computed according to 0.8µm oxide thickness.

The MOS Model 3
For the evaluation of the current Ids as a function of Vd,Vg and Vs between Drain and Source, we commonly use the following equations, close from the SPICE model 3 formulations. The formulations are derived from the model 1 and take into account a set of physical limitations in a semi-empirical way.
CUT-OFF MODE. Vgs<0

Ids = 0
NORMAL MODE. Vgs>Von


Ids = Keff (1+KAPPA vds) Vde ((Vgs-vth)- ))

with


von = 1.2 vth

vth = VTO + GAMMA(- )

vde = min ( vds, vdsat)

vdsat = vc + vsat -

vsat = vgs-vth

vc = VMAX

LEFF = L - 2 LD

Keff =


SUB-THRESHOLD MODE. Vgsvds is replaced by von in the above equations.

Ids = Ids(von,vds) e

In those formulas, W corresponds to the MOS channel width, L to the MOS channel length and VTO to the threshold voltage. The KP parameter is evaluated by the following formula in which : µn is the mobility of electrons, µp the mobility of holes, and TOX the gate oxide thickness.
KP(n) = µn e0 eS / TOX

KP(p) = µp e0 eS / TOX


where (0.8 technology)
µn = 510 V.cm-2 µp = 270 V.cm-2

er (SiO2)= 3.9 e0 = 8.85 e -14 Farad/cm

TOX = 150 nm

n = 2


k = 1.381e-23

T = 300 °K

q = 1.6e-19

Temperature effects :


µn = µn0 (T-300) e(-1.5)

µp = µp0 (T-300) e(-1.5)

vt = vt0-0.002(T-300)

Tutorial on SPICE Level 3 Parameters

Click on the MOS characteristics icon. The screen displays the Id/Vd simulation of the nMOS device. You can change the MOS parameter values directly on the screen and see the effect on the MOS simulation. Notice that KP includes the values of TOX (thin-oxide thickness) and of U0 (the carrier mobility) as described in the previous chapter.
Fitting the model with measurements
Click on Add Measurement. The program scans the current directory and displays the list of measurement files with and appendix called ".MES". Choose Es207_n20x20.MES. It corresponds to the measurements performed on a real MOS device with size W=20 µm, L=20 µm, fabricated by ATMEL ES2 in their 0.8 µm technology (ES208.RUL). You should always start with measurements for a device with a very large width and length. The second order effects are reduced in such devices. The measured data is added to the drawing, as shown in the Figure 9.


Fig. 9. The measured data file is added to the simulation (Es207_20x20.MES file).
The principles for fitting the simulation with the measurements are described below.
ΠClick on Id vs. Vg. The curve shown in Figure 10 is used to fit VTO and Decrease VTO down to 0.7 in order to shift the curves to the right, and increase GAMMA up to 0.65 to adjust the set of curves. The measurement step for vbulk is 1.0V while the simulation step is 0.5 V in the figure.



Fig. 10. The Id/Vg to find VTO and fit GAMMA (Es207_20x20.MES file).

 Click on Id vs. Vd. Increase THETA to bend the curve in order to find a compromise. Although not satisfactory, the result is quite correct.



Fig. 10. Fitting the model with the measured data file (Es207_20x20.MES file).
 Now load a new measurement such as Es207_N20x0,8.mes. Click on Id vs. Vg Increase LD in order to fit the slope in the Id/Vg curve.

Fig. 11. Small channel MOS measurement (Es207_20x0,8.MES file).
 Click on Id vs. Vd. Adjust VMAX to fit the transition point between the linear and the saturated region according to the measurement. Next, adjust KAPPA to adapt the positive slope in the saturated region.


Fig. 11. Small channel MOS measurement (Es207_20x0,8.MES file).

Ž Click on Id(log)/Vg. Verify that the slope is correct in sub-threshold mode. If not you can adjust the slope using NSS. Notice that the measurement limit is in the order of the nA. This is why no reliable data is available below 10-9 A (Figure 12).



Fig. 12. Small channel MOS measurement in the sub-threshold region (Es207_20x0,8.MES file).

The PMOS Transistor
The p-channel transistor simulation features the same functions as the n-channel device. Click on pMOS in the menu. The software switches to the p-channel MOS simulation, as shown in Figure 13. Note that the pMOS gives only half of the maximum current given by the nMOS with the same device size.

Fig. 13. Simulation of the p-channel MOS.

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