Tallinn, 21. mai 2003 Kuidas tagada kvaliteeti üha keerukamates digitaalsüsteemides

Tallinn, 21. mai 2003 Kuidas tagada kvaliteeti üha keerukamates digitaalsüsteemides

• Raimund Ubar

• TTÜ

• [e-mail]

• www.ttu.ee/ˇraiub/

Outline

• Introduction to Digital Test
• Test as the quality problem
• Defect and fault models
• Hierarchical approach to test
• Decision Diagrams (beyond BDDs)
• Overview of tools developed at D&T Lab
• Conclusions

Introduction

Introduction – Test Tools

Introduction – Test Generation

• A fault a/0 is sensitisized by the value 1 on a line a

• A test t = 1101 is simulated, both without and with the fault a/0

• The fault is detected since the output values in the two cases are different

• A path from the faulty line a is sensitized (bold lines) to the primary output

Introduction – Fault Simulation

Introduction – Fault Diagnosis

Test as the Quality Problem

Test as the Quality Problem

How Much to Test?

How Much to Test?

• Paradox:

• 264 input patterns (!)
• for 32-bit accumulator
• will be not enough.
• A short will change the circuit
• into sequential one,
• and you will need because of that
• 265 input patterns

• Paradox:

• Mathematicians counted that Intel 8080
• needed for exhaustive testing 37 (!) years
• Manufacturer did it by 10 seconds
• Majority of functions will never activated
• during the lifetime of the system

How to Generate a Good Test?

• Paradox:

• To generate a test
• for a block in a system,
• the computer
• needed
• 2 days and 2 nights
• An engineer
• did it by hand
• with 15 minutes
• So, why
• computers?

Complexity vs. Quality

• Problems:

• Traditional low-level test generation and fault simulation methods and tools for digital systems have lost their importance because of the complexity reasons

• Traditional Stuck-at Fault (SAF) model does not quarantee the quality for deep-submicron technologies

• How to improve test quality at increasing complexities of today's systems?

• Two main trends:

• Defect-oriented test and
• High-level modelling

• Both trends are caused by the increasing complexities of systems based on deep-submicron technologies

Towards Solutions

• The complexity is handled by raising the abstraction levels from gate to RTL, ISA or behavioral levels

• But this moves us even more away from the real life of defects (!)

• To handle defects in deep-submicron technologies, new defect-oriented fault models and test methods should be used

• But, this is increasing even more the complexity (!)

• As a promising compromise and solution is:

• To combine hierarchical approach
• with defect orientation

Outline

• Introduction to Digital Test
• Test as the quality problem
• Defect and fault models
• Hierarchical approach to test
• Decision Diagrams (beyond BDDs)
• Overview of tools developed at D&T Lab
• Conclusions

Fault and defect modeling

• Defects, errors and faults

• An instance of an incorrect operation of the system being tested is referred to as an error

• The causes of the observed errors may be design errors or physical faults - defects

• Physical faults do not allow a direct mathematical treatment of testing and diagnosis

• The solution is to deal with fault models

Fault and defect modeling

• Why logic fault models?

• complexity of simulation reduces (many physical faults may be modeled by the same logic fault)

• one logic fault model is applicable to many technologies

• logic fault tests may be used for physical faults whose effect is not completely understood

• they give a possibility to move from the lower physical level to the higher logic level

Transistor Level Faults

Mapping Transistor Defects to Logic Level

Mapping Transistor Faults to Logic Level

Functional Fault vs. Stuck-at Fault

Generalization: Functional Fault Model

• Constraints calculation:

Fault Table: Mapping Defects to Faults

Outline

• Introduction to Digital Test
• Test as the quality problem
• Defect and fault models
• Hierarchical approach to test
• Decision Diagrams (beyond BDDs)
• Overview of tools developed at D&T Lab
• Conclusions

First Step to Quality

• How to improve the test quality at the increasing complexity of systems?

• First step to solution:

• Functional fault model

• was introduced

• as a means

• for mapping physical defects

• from the transistor or layout level

• to the logic level

Faults and Test Generation Hierarchy

Hierarchical Test Generation Approaches

• Bottom-up approach:

• Pre-calculated tests for components generated on low-level will be assembled at a higher level

• It fits well to the uniform hierarchical approach to test, which covers both component testing and communication network testing

• However, the bottom-up algorithms ignore the incompleteness problem

• The constraints imposed by other modules and/or the network structure may prevent the local test solutions from being assembled into a global test

• The approach would work well only if the the corresponding testability demands were fulfilled

Hierarchical Test Generation Approaches

• Top-down approach - to solve the test generation problem by deriving environmental constraints for low-level solutions.

• This method is more flexible, since it does not narrow the search for the global test solution to pregenerated patterns for the system modules

• The method is of little use when the system is still under development in a top-down fashion, or when “canned” local tests for modules or cores have to be applied

Two trends:

• Two trends:

• high-level modeling

• to cope with complexity

• low-level modeling

• to cope with physical defects, to reach higher acuracy

Outline

• Introduction to Digital Test
• Test as the quality problem
• Defect and fault models
• Hierarchical approach to test
• Decision Diagrams (beyond BDDs)
• Overview of tools developed at D&T Lab
• Conclusions

Binary Decision Diagrams

Low-Level Test Generation on SSBDDs

• Test generation for a bridging fault:

Test Generation on High Level DDs

Hierarchical Test Generation on DDs

High Level Fault Models

Fault Modeling on High Level DDs

• High-level DDs (RT-level):

DECIDER: Hierarchical ATPG

ATPG: Experimental Results

TURBO-TESTER: Low-Level TPG Tools

Conclusions

• Traditional low-level test generation and fault simulation methods and tools for digital systems have lost their importance because of the complexity reasons
• As a promising compromise and solution is: to combine hierarchical approach with defect orientation
• Still three problems remain open:
• defects in the interconnection network cannot be preanalyzed and described in the component libraries
• combining the low-level solutions with high-level solutions in the hierarchical approach is often not possible because of the inconsistencies of signals
• design for testability to enable the hierarchical approach is not always accepted because of the area overhead and performance restrictions
• BIST provides an alternative to the functional testing on hierarchical principles

Conclusions of our Research Experience