The Inter-Frame Gap module was implemented to calculate the IPG (inter-packet gap)
between the received frames. This module was implemented using a finite state machine
and CAM (content accessible memory). The Block Select RAM primitive with data
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width 16 bits and depth 16 words was used to generate a CAM using Xilinx’s core
generator. The contents for the memory are specified in a text file. The text file contains
different combinations of Start and Terminate data. During implementation the values
will be embedded in the EDIF netlist. A match signal is asserted whenever the data on the
input bus matches the data in one of the locations in the CAM. The FSM (finite state
machine) checks if the data is a Terminate character or a Start character. If the data is a
terminate character, it starts incrementing the counter until it sees a next match for Start
character. The inter packet gap is determined by the counter value. After seeing the
match for the start character a second counter starts incrementing until it sees a terminate
character. The value of the second counters gives the frame size. Error patterns can also
be written to the memory contents of the CAM. Whenever the input data matches the
error contents, a flag-bit is set high to indicate error. This module was verified
functionally using Modelsim and Verilog test benches. The module was embedded into
the previous test system and was verified on the ML321 board.
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