JCTVC-J0292 Suggested figures for HEVC specification [C. Fogg (Harmonic)]
This proposal suggests the addition of a few diagrams not currently in the draft HEVC specification 1) Overall decoder stages to establish the logical flow order, in particular the sequential loop filters (DF, SAO, ALF); 2) an illustration showing the possible generic (non-profile/level specific) block shapes for CU, TU, PU ; 3) the possible transform types and sizes. While pseudo-code and specification language written in a literal manner that could be assembled into meaning by a compiler has its uses (contractdisputes, artificial intelligence, natural language to Verilog/VHDL translators..), collective studies show that human understanding improves with visual aides that engage a larger area of the cortex analyzing spatial relationships than the networks integrating just the processing islands of non-symbolic language and logic.
It was agreed that having more figures may be desirable, if feasible – provided the figures are correct. The consideration of this input was delegated to the editor.
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