Comparator The truth table and the schematic diagram of the comparator are given below. The A=B equality represents an XNOR gate, and A>B, ACOMPARATOR
A B A>B A
0 0 0 0 1
0 1 0 1 0
1 0 1 0 0
1 1 0 0 1
Fig. 42. The truth table and schematic diagram of the comparator (COMP.SCH).
Using DSCH, the logic circuit of the comparator is designed and verified at logic level. Then the conversion into Verilog is invoked (File -> Make verilog File). Microwind compiles the verilog text into layout. The layout and simulation of the comparator is given in Figure 43. The XNOR gate is located at the left side of the design. The inverter and NOR gates are at the right side. After the initialization, A=B rises to 1. The clocks A and B produce the combinations 00,01,10 and 11. Notice the small glitch on A>B at t=12 ns. This glitch is not a design error. On the contrary, it shows that during the transition of A and B the situation A>B occurs and that the cell is fast enough to react.
Fig. 43. Simulation of a comparator (COMP.MSK file).
5. Latches and Memories
RS Latch The RS Latch is made up of two interconnected NAND gates. The Reset and Set inputs are active low. The memory state corresponds to Reset=Set=1. The combination Reset=Set=0 should not be used.
R S Q nQ
0 0 X X
0 1 0 1
1 0 1 0
1 1 Q nQ
Fig. 44. The truth table and schematic diagram of a RS latch made from 2 NAND gates (RS.MSK).
DESIGN. You can use the VERILOG compiler for the creation of the RS latch with cell declarations as follow. See « rs.txt » text file.
Fig. 45. The design of a RS latch made from 2 NAND gates (RS.MSK).
SIMULATION. Assign a negative pulse to R. The pulse icon is one of the simulation icons and is shown below. Select this icon, then click near the Reset label. The pulse parameter window appears. The default pulse is positive. Invert the voltage cursors situated on the left of the window in order to program a negative pulse.
Assign another negative pulse to Set. The pulse is automatically delayed from the previous pulse assigned to Reset. Click on Simulatein the main menu. The timing diagrams appear as reported in Figure 46.
The simulation steps are the following:
Inputs R and S are fixed to 1. The latch is in a memory state.
A negative pulse is applied to R. The latch output Q goes to a level of 0.
A short time after, a negative pulse is applied to S. The latch output Q goes to 1.
Fig. 46. The simulation of a RS latch (RS.MSK). D Latch The truth table and schematic diagram of the static D latch, also called Static D-Flip-Flop, are shown in Figure 47. The data input D is transferred to the output if the clock input is at level 1. When the clock returns to level 0, the latch keeps its last value.
D H Q nQ
0 0 Q nQ
1 0 Q nQ
0 1 0 1
1 1 1 0
Fig. 47. The truth table and schematic diagram of a D Latch (File DLATCH.MSK).
MANUAL DESIGN. Use the one line compiler to create successively one inverter nd=/d, and two complex gates which include the AND/NOR cells using the syntax Q=/(nQ+(nd.h)) and nQ=/(Q+(d.h). Build the interconnections and run the Design Rule Checker. Assign a clock to H and a clock to D.
VERILOG COMPILING. Compile the cells using the following description file « dlatch.txt ».
Otherwise you can load a design of the D-latch using the commands File -> Read-> DLATCH.MSK(Figure 48).
Fig. 48. The design of a D-latch (DlatchLevel.MSK). SIMULATION. Click on Simulate of the main menu. The timing diagrams appear as reported in Figure 49. The simulation steps are listed below :
The clock H is at level 0 so that the latch can be in a memory state.
The input D changes. Nothing changes in the output.
The clock H goes to level 1. The output Q copies the input D.
The clock H goes back to level 0. The output Q keeps its last value.
Fig. 49. The simulation of a D-latch (DLatchLevel.MSK). RAM Memory The schematic diagram of the static memory cell used in High Capacity Static RAMs is given in Figure 50. The circuit consists of 2 cross-coupled inverters and two nMOS pass transistors. The cell has been designed to be duplicated in X and Y in order to create a large array of cells. Usual sizes for Megabit SRAM memories are 256 x 256 cells or higher. The selection line Sel concerns all the cells of one row. The lines Data and nData concern all the cells of one column.
Fig. 50. The schematic diagram of the static RAM cell (RAM.MSK).
The RAM layout is given in Figure 64. Click on File -> Read -> RAM.MSK to read it. The Data and nData signals are made with metal and cross the cell from top to bottom. This allows easy matrix-style duplication of the RAM cell.
Fig. 51. The layout of the static RAM cell (RAM.MSK). WRITE CYCLE. Values 1 or 0 must be placed on Data, and the data inverted value on nData. Then the line Sel goes to 1. The two-inverter latch takes the Data value. When returning to 0, the RAM is in a memory state.
READ CYCLE. In order to read the cell, the line Sel must be asserted. The RAM value propagates to Data, and its inverted value propagates to nData.
SIMULATION. The simulation parameters correspond to the write cycle in the RAM. The simulation steps are as follows :
Mem reaches 1, nMem 0 (unpredicatable value).
Data gets to value 1 and nData to value 0.
Sel is asserted. The memory cell reaches stays at 1.
Data gets to a value of 0 and nData gets to a value of 1.
Sel is still asserted. The memory cell gets 0.
. Sel is inactive. The RAM is in a memory state.
Fig. 52. Write cycle for the static RAM cell (RAM.MSK).
Complete RAM 4x4 Bit You can duplicate the RAM cell into a 4x4 bit array using the command Edit -> Duplicate XY. Select the whole RAM cell and a new window appears. Enter the value « 4 » for X and « 4 » for Y into the menu. Click on « Generate ». The result is shown below.
Fig. 53. Duplicating the RAM Cell in X and Y The column decoder is based on the following schematic diagram. One line is asserted while all the other lines are at zero. In this circuit one line was picked out from a choice of four lines. Using AND gates would be an easy solution, but in order to save the inverter, we chose NOR gates with inverted inputs.
Fig. 54 - a. A line selection circuit
Fig. 54- b . A line selection layout and its corresponding simulation (RamLineSelect.MSK)
The NOR gate height should be adjusted to that of the RAM cell height. When making the final assembly between blocks, the command Edit -> Move Area is very important. This command helps to move a selected block with a lambda step.
The row decoder is based on the same principles as those of the line decoder. The major modification is that the data flows both ways, that is firstly from the cell to the read circuit (Read cycle) and secondly from the write circuit to the cell (Write cycle). Fig. 55 proposes an architecture for this.
The n-channel MOS device is used as a switch controlled by the column selection. When the n-channel MOS is on and Write is asserted, the data issued from DataIn is amplified by the buffer, flows from the bottom to the top and reaches the memory. If Write is off, the 3-state inverter is in high impedance, which allows one to read the information.
Fig. 55. Row selection and Read/Write circuit (RamRow.MSK) The final layout of the RAM 4x4 is proposed in Fig. 56. The simulation proposes the read and write cycles at a specific RAM cell address.
Fig. 56. RAM 4x4 layout and simulation (Ram44.MSK)
The simulation of Fig. 56 can be described as follows. A  fixed line selection selects the upper line, that way « sel0 » is asserted while all others are at 0. The memory cells mem00 and mem01 do not reach the same initial state : mem00 gets to 0 and mem01 is at 1. When DataIn is at zero, writing a zero has no effect on Mem00. But when the column selection changes, DataIn=0 is copied to Mem01.
When DataIn rises to 1 (t=10ns), and when write is 1, the memory cells change from 0 to 1. It is interesting to point out that the memory cell fights against the logic value before surrending and changing its internal state.
6. Other Projects
This section expounds some typical layout projects and presents the general design principles for the layout of each project. The latter are ready-to-simulate items. They can be simulated in any technology, from 1.2µm to 0.12µm. Below is how to proceed :
Select the filename,
Notice that most of those layouts are complex and require a significant amount of time for extraction and for simulation.
Four-Bit Adder This circuit include one half-adder and three full-adders (See Figure 57). The result of each stage propagates to the next one, from the top to the bottom. The circuit allows a four-bit addition between two numbers A3,A2,A1,A0 and B3,B2,B1,B0. Figure 58 details the four-bit adder layout, and Figure 59 shows the corresponding simulation.
4 BIT Adder (ADD4.MSK)
Fig. 57. Schematic diagram of the four-bit adder (ADD4.MSK).
Fig. 58. Design of the four-bit adder (ADD4.MSK).
Fig. 59. Simulation of the four-bit adder (ADD4.MSK).
2x 2 Bit Multiplier The multiplier cell is made up of a full-adder cell and a NAND gate. The cell is built for an iterative implementation, and a 2x2bit multiplication is proposed. The circuit multiplies input A (2 bits) with input B (2 bits) which produces a result P, as detailed in Figure 60. The circuit design is complex and the simulation takes a lot of time. The multiplier layout is shown in Figure 61. In the simulation of Figure 62, the multiplication time is 5nS in the worst case.
Fig. 60. Truth table and schematic diagram of the 2x2 bit multiplier (MUL22.MSK).
Fig. 61. Design of the 2x2 bit multiplier (MUL22.MSK).
Fig. 62. Simulation of the 2x2 bit multiplier (MUL22.MSK). Two-Bit Counter The one-bit counter is a static register controlled by a single clock H. Its schematic diagram is shown in Figure 63. In order to build a two-bit counter we used two counter cells that we have interconnected as follows: the clock of the second stage is the output of the first one. The clocks H and nH changes the state of C0 at each rising edge. The clock C0 changes the state of C1 at each rising edge. The outputs C0 and C1 make a 2-bit counter. The layout is reported in Fig. 64 and its corresponding simulation is shown in Figure 65.
Fig. 63. Schematic diagram of the 2-bit counter (DivFreq.MSK).
Fig. 64. Design of the 2-bit counter (DivFreq.MSK).
Fig. 65. Simulation of the 2-bit counter (DivFreq.MSK).
Wide-Range Amplifier The wide-range amplifier is built using a voltage comparator and a power output stage. Its schematic diagram is reported in Fig. 66. The difference between V+ and V- is amplified and it produces a result, codified : Vout. The gain near 2.5V is more than 1,000. Use the Voltage vs. Voltage simulator mode to get the transfer characteristics Vout/V+. The input range is around 0.5Vto 4.0V.
You can easily build a follower by designing an extra connection from Vout to V-. This layout is shown in Figure 66. The output stage is not strong enough to be able to drive large loads such as output pads.
WIDE RANGE AMPLIFIER
V+ Positive analog input
V- Negativeanalog input
Vbias Bias voltage
Vout Analog output
Fig. 65. Node description and schematic diagram of the analog amplifier (AMPLI2.MSK).
. Fig. 66 Design of the analog amplifier (AMPLI2.MSK).
Fig. 67. Transient simulation of the analog amplifier (AMPLI2.MSK) connected as a follower
Fig. 68. DC Simulation of the analog amplifier (AMPLI2.MSK) in follower mode, using voltage vs. Voltage mode.
Interface with PSPICE The simulation of the transient and DC characteristics of the amplifier can be performed using Microwind. Unfortunately the AC response cannot be computed. The command File -> Make Spice File converts the design into a PSPICE compatible description based on MOS devices and parasitic capacitances (Fig. 69).
Fig. 69. Generation of the file AMPLI2.CIR compatible with SPICE Figure 69 depicts the interface window. The left part of the window details the list of MOS devices with their associated width and length in lambda unit. The right part lists the contents of the PSPICE compatible file, "AMPLI2.CIR" generated from the electrical extraction of the layout « AMPLI2.MSK ».
To obtain the AC response of the amplifier, the AMPLI2.CIR source file must be modified as follows: an AC source must be declared (Choose the input V+ and add "AC 1 0"), and the .TRAN mode must be replaced by .AC DEC 10 1K 100MEG for example (AC analysis, 10 points/decade, from 1KHz to 100MHz). Run PSPICE and see the result. The DB mode is drawn using the command VDB(output node) in the PLOT command "Add Trace".
Analog-Digital Converter The analog-digital converter converts an analog value Vin into a two-bit digital value called A0,A1. The flash converter uses three converters and a coding logic to produce A0 and A1 (Figure 70). A very complex logic circuit and 255 comparators would be used for an ADC eight-bit flash.
The polysilicon has a high resistance (50 per square) and can be used as a resistor network (Left of Figure 71), which generates intermediate voltage references used by the voltage comparators located in the middle. The resistance symbol is inserted in the layout to indicate to the simulator that an equivalent resistance must be taken into account for the analog simulation.
Open-loop amplifiers are used as voltage comparators. The comparisons address the decoding logic situated to the right and that provides correct A0 and A1 coding.
V Analog input
C0 Result of comparison with 1.25V
C1 Result of comparison with 2.5V
C2 Result of comparison with 3.75V
A1 Digital output
A0 Digital output
Fig. 70. Node description and schematic diagram of the analog-digital converter (ADC.MSK).
Fig. 71. Design of the analog-digital converter (ADC.MSK).
Fig. 72. Simulation of the analog-digital converter (ADC.MSK). In the simulation shown in Figure 72, the comparators C0 and C1 work well but the comparator C2 is used in the upper limit of the voltage input range. The generation of combinations 00,01 and 10 is correct. The generation of 11 is slow.
Digital-Analog Converter The digital-analog converter converts a digital three-bit input (A0,A1,A2) into an analog value Data. The polysilicon resistive net gives intermediate voltage references which flow to the output via a transmission gate net. The resistance symbol is inserted in the layout to indicate to the simulator that an equivalent resistance must be taken into account for the analog simulation.
The schematic diagram is shown in Figure 73. The layout of the digital-analog converter is shown in Figure 74.
DIGITAL ANALOG CONVERTER
Ai Input Ai
nAi Inverted input Ai
Vout Analog output
Fig. 73. Node description and schematic diagram of the digital-analog converter (DAC.MSK).
Fig. 74. Design of the digital-analog converter (DAC.MSK)
Fig. 75. Simulation of the digital-analog converter (DAC.MSK). The simulation of the DAC (Fig. 75) shows a regular increase of the output voltage Vout with the input combinations, from 000 (0V) to 111 (4.375V). Each input change provokes a capacitance network charge and discharge.
Input-Output Pad Interfacing We give here some details about input-output pad interfacing. The basic bonding pad size is 100x100µm. The pad consists of a sandwich of metal2, via and metal1 layers. For advanced technologies, all metal layers are stacked on the top of each other. Use the process simulator to verify that the passivation oxide has been removed from over the pad, so that a gold connection can be fixed upon it.
The input-output pad contains one input stage with a polysilicon resistor and two protection diodes. The output stage contains a chain of inverters. The last stage is a 3-state inverter so that the buffer can be turned off.
Vout Digital output value
EN Enable digital output
nEN Inverted Enable digital output
Data Pad input value
Fig. 76. Design of an input-output pad (PAD.MSK) Pad Ring
Click on the chip library icon and click on Pads. The window reported in Fig. 77 appears. Select the size 100x100 µm which enables the pad ring options. A pad ring with 3 pads in X and 3 pads in Y is generated by a click on Generate Pad. In that case, a set of pads is added to your circuit. The VSS pad is situated at the bottom, and the VDD pad at the top with the associated power rings.
Fig. 77. Pads added to generate a pad ring around the chip. Figure 78 displays an example of circuit with its input-output pads and interconnects. The chip contains a pad ring of 28 input/outputs (CHIP.MSK file).
Fig. 78. A complete chip with I/O pads and internal logic and analog cells (CHIP.MSK)
ESD Protections The input pad includes some voltage boosting and under voltage protections linked with problems of electrostatic discharge (ESD). Such protections are required as the oxide of the gate connected to the input could be destroyed by over voltage. One of the most simple ESD protection is made up of a set of two diodes and a resistance (Fig. 79). One diode handles the negative voltage flowing inside the circuit (N+/P substrate), the other diode (P+/N well) handles the positive voltage.
The layout of the N+/P_Substrate diode includes a simple N+ diffusion in the P- substrate (the cathode K), surrounded by P+ contacts which polarize the P- substrate (the anode A). The current starts flowing between A and K if the voltage is roughly over 0.6V. In the reverse mode, the current is very small, in the order of some pico-Ampere. The polarization of the P- substrate is usually 0V. The diode N+/P- will be on if the voltage of the N+ region is less than -0.6V.
Fig. 79. Detail of the Input protection used against electrostatic discharge (CHIP.MSK) One simple way to add a diode in the layout is to click on the cell library icon, then click on the Contacts menu and to assert the options : « Diffp/Metal » and «Diff N+ on Nwell ». This creates a P+/Nwell diode with its appropriate contacts (Fig. 80).
Fig. 80 -a : Create a diode based on a Diffp/Metal contact in nwell
Fig. 8- b :. Create a diode for I/O pad protections