Ep optima synopsis

The project will provide telecommunication equipment manufacturers with the capability to integrate using a single ASIC all the baseband and control circuitry of a digital radio terminal compliant with the TETRA and TETRAPOL standards. These terminals represent 30% of the private mobile radio (PMR) market, and this projects enables lightweight terminals with long battery life to be realised.

Key analogue elements of the project are the Mixed-Signal Cells, I/Q RF Codec and CCITT Voice Codec. The analogue work will build on the design know how and the cells produced in ALCD Project, ESPRIT 8030 which now form part of ATMEL’s pre-characterised standard cells library.

Digital design will focus on integrating the ARM7TDSP combined controller/DSP (Thumb/Picollo) core which provides a state-of-the-art performance and low power dissipation for implementing the control and baseband processing functions. This work will also include further development of the real-time operating systems and high level language programming tools to enable optimised algorithmic-level DSP compilation.

Objectives

· Realisation of analogue and digital building blocks targeted to ASIC implementation of control and baseband processing for TETRA/TETRAPOL private mobile radio systems;

· Realisation of single chip control and baseband processing ASIC integrating analogue, embedded controller and digital signal processing function blocks;

· Development and demonstration of an enhanced real-time operating system and debugger for the target applications;

· Development and demonstration of an optimising compiler for the Picollo DSP core;

· Development of user development boards;

· Partners, Matracom and OTE, will incorporate the ASICs into terminal demonstrators for the TETRAPOL and TETRA systems respectively.

Participants

ATMEL (F), ARM (UK), THERA (I), IST (P), Matracom (F), OTE (I)
Contact Point Duration

Ben Altieri, 24 months from 01.12.96

ATMEL/ES2

13106 Rousset Cedex, (France)
Tel: [phone]

Fax: [phone]

E-mail: [e-mail]

EP 24006 SPACE

SOI for Portable Applications and Consumer Electronics
Summary

A cost effective production process developed by LETI to produce SOI (Silicon on Insulator) wafers, with very low defect density, is at the origin of this project. In the SOI approach, the oxide layer under the drain and the source of the MOS transistors considerably reduces the parasitic capacitance of inverters and gates, especially at low supply voltages (below 1V) where the junction capacitance starts to increase exponentially. So below 1V the low power advantage of SOI is dominant and the cost per SOI transistor will be equal to the cost of a bulk CMOS-epitaxial transistor.

The reduced parasitics also give SOI technology superior RF capabilities to bulk CMOS.

The objective of the project is to develop the 0.25m SOI technology at LETI in Grenoble and to transfer it to the production fab of ST in Crolles. The capabilities of the technology will be demonstrated with a GSM receiver -from RF to a serial digital I/Q baseband interface- by Alcatel, with some design activities subcontrated to Dolphin and Swindon Silicon Systems.UCL will contribute to the project with modelling of transistors and passives.

Objectives

· Perform a technical demonstration of the core CMOS/SOI technology at 1.8V supply voltage on a 200mm wafer.

· Develop passive components (resistors, capacitors, inductors) on SOI for analogue functions.

 Measure HF characteristics of the technology and the dynamic performance in terms of speed, maximum frequency, power consumption and crosstalk.

 Develop a complete design kit for mixed A/D applications.

 Design the specific building blocks for a single chip GSM receiver.

 Prepare the industrialisation and study the cost of ownership, reliability, quality, cost and volume production conditions of 200mm SOI.

 Demonstrate full integration of the 0.25m mixed A/D CMOS/SOI technology at the IC manufacturer site.

 Perform the demonstration of feasibility of a single chip radio-telephone function for the 900MHz GSM portable telephone applications.
Participants__Alcatel_(B)'>Participants

Alcatel (B), SGS-Thomson (F), LETI (F), UCL (B)

Contact Point Duration

Jan Sevenhans 30 months from 01.01. 97

ALCATEL BELL

Francis Wellesplein 1

2018 ANTWERPEN (Belgium)
tel: [phone]

fax: [phone]

E-mail: [e-mail]

EP 24123 OCMP

One-Chip Low Power Transceiver for
Multi-Mode Portable Phones
Summary

The OCMP project will apply proven analog low power design techniques to develop a single chip radio frontend for multi-mode (DCS1800 & DECT standards) hand portable terminal. It will include frequency synthesizer components, up/down converter blocks and amplifier blocks, such as LNA and prepower amplifier. The aim of the project is to prepare the way for the commercial availability of such an innovative component assisting significantly the small system companies which manufacture portable terminals and wish to enter the multi-mode terminal market.

Objectives

• 
  The main objective of the OCMP project is to provide the market with a highly integrated low power transceiver chip, which addresses two modes of operation, DCS1800 and DECT, and can be used in future generation multi-mode terminals. The chip will contain high frequency bipolar circuits including frequency synthesizer components, up/down converting mixers, 90⁰ phase shifters, LNA, etc.
  
• 
  The direct conversion architecture will be adopted for the transceiver, thus allowing the maximum possible integration and, compared to the classical heterodyne approach, requiring fewer external components.
  
• 
  A single mode DECT transceiver chip with direct conversion architecture will also be developed. This development, combined with existing partners’ research results in a DCS1800 transceiver test chip development, will contribute to the definition of the multi-mode transceiver chip specifications.
  
• 
  Compliance to DECT and DCS1800 modes will be demonstrated using the multi-mode transceiver chip in a multi-mode terminal demonstrator by verifying proper operation in each individual mode.
  
• 
  The extension of the transceiver chip to the GSM standard will be studied.
  

Participants__Alcatel_Mietec_(B)'>Participants__SGS-Thomson_Microelectronics_(F)'>Participants

Intracom (GR); SGS-Thomson Microelectronics (I), Telital (I), Swindon Silicon Systems (UK)
Contact Point Duration

Mr. Dimitris Dervenis 30 months from 01.01.97

INTRACOM S.A.

19,5 km Markopoulou Ave

19002 Peania, (Greece)
Tel: [phone]

Fax: [phone]

E-mail: [e-mail]

EP 21587 STARLIGHT

The Starlight Core for Express Disk Drive Controllers
Summary

The trend in the drive industry is towards higher integration of disk functions into fewer monolithic devices. Current drive designs use 16-bit micros; in multiple high-density devices, performing drive functions such as servo control, disk control, host control and read/write data transfer. In the move towards a 'drive-on-a-chip', these micros cannot deliver the processing bandwidth necessary to carry out these real-time functions.

New 32-bit architectures such as the ST20 have five to ten times the processing power of the current micro solutions being used. In addition, the integration of DSP-type functions such as hardware multipliers further relieves the processing burden on the micro-core. By upgrading to machines such as the ST20, the disk architect benefits from MIP increases due to more efficient instruction sets; greater data bandwidth and DSP functionality.

The processing benefits of a 32-bit move have been evident for some time. The drive industry has applied pressure on microprocessor architects to provide the functionality described above, but at a cost in die area that was not feasible in the industry. Starlight is to demonstrate that these issues can be successfully addressed by the ST20 and that the time is now right for this 32-bit move.

Objectives

· Design and manufacture a reduced-size micro-core (STARLIGHT core) optimised for disk drive applications.

· Develop a family of disk drive subsystems to enable silicon integration for customer specific solutions.

· Produce an integrated simulation model (VHDL) of the STARLIGHT core family with application specific subsystems developed for the disk drive controller. This will provide a prototype to demonstrate the state-of-the-art 32-bit solution to potential customers.

· Development of software support for STARLIGHT core applications. Suitable software support to allow systems to be developed and debugged together with the necessary compiler development to target the reduced instruction set core.
Participants

SGS-Thomson Microelectronics (F), Silicon Systems Designs (IRL)
Contact Point Duration

Victoria Griffiths 18 months from 15.04.96

SGS Thomson Microelectronics Ltd

1000 Aztec West

Almondsbury

Bristol BS12 4SQ (United Kingdom)
tel: [phone]

fax: [phone]

EP 23223 SCHINET

Single Chip ISDN Network Termination
Summary

ISDN constitutes an important step in providing links which connect society to the information highway by expanding the bandwidth of the standard telephone gateway to a rate of four times higher than a sophisticated modem.

In this project Alcatel Mietec and Quante will join forces to develop circuit techniques and macroblocks which can be used to create a high performance single chip ISDN Network Terminator. The resulting chips will cut costs and power dissipation down to the level required for open market proliferation. This mixed-mode ASIC will contain advanced design techniques that combine complex digital circuit of up to 300,000 transistors including embedded data processors together with high performance analogue circuits delivering 12 bit accuracy at 15MHz sampling speeds.
Objectives

· Development of a single-chip Network Terminator for ISDN with minimum pincount and external components incorporating the following characteristics.

- fully ANSI and ETSI compliant U interface

- fully ITU compliant S interface

- two wire transmission NRZ 2B1Q 64 and 144 kbits/sec

- maintenance and service information signalling, possibility to

read out the state and coefficients

- automatic polarity adaptation, automatic gain control

- DSP with adaptive echo cancellation and decision feedback equalisation

- evaluation of the sampling instant by digital phase-locked-loop

- fast return to operation after line seizure due to data storage during
power down state, activation and deactivation including loop-control

- GCI interface for extended applications (NT plus mode)

· Key macroblocks developed within the project will be accessible to third parties via the Alcatel-Mietec design library.

Participants

Alcatel Mietec (B), Quante (D)
Contact Point Duration

Dr. Edmond Janssens 18 months from 01.10.96

Alcatel Mietec

Westerring 15

B 9700 Oudenaarde (Belgium)
Tel: [phone]

Fax: [phone]

E-mail: [e-mail]

EP 24137 TWIST
Twin Carrier Single Transceiver Base Station for PCS
Summary

In radio local-loop (RLL) applications for dense scenarios, traffic is the most demanding parameter. This is in contrast to a low density scenario where coverage is of paramount importance. The maximum amount of traffic handled in a cell site is limited by the handling capabilities of the installed equipment and by the level of interference caused by users in the cell or adjacent cells.

Analysis of cost/traffic ratios leads to the conclusion that an optimal configuration corresponds to the colocation of two transceivers per sector. The TWIST project intends to further improve this solution.

The goal of the project TWIST is to develop the core device of a novel DECT transceiver architecture capable of supporting two simultaneous communications (in TDD systems) requiring one single RF front-end. The architecture is based on the principle of image separation.

Objectives

There are two objectives :

• 
  To develop the core component for a double channel single transceiver base station.
  

• 
  To demonstrate the functionalities of the device as well as the feasibility of the concept. A demonstrator will be built and laboratory measurements will be carried-out and reported.
  

Participants

Alcatel Standard Eléctrica S.A. (E); Universidad Politécnica de Madrid (E); Swindon Silicon Systems Ltd (UK); Alcatel Mietec (B).
Contact Point Duration

Alfonso Fernández-Durán, 24 months from 01.01.97

Alcatel Standard Eléctrica S. A.

Ramírez de Prado, 5

Madrid 28045 (Spain)
Tel: [phone]

Fax: [phone]

e-mail: afd @alcatel.es

EP 26320 IN-RAM

Intelligent RAM Component for Streaming Applications