Ep optima synopsis

Participants

Thesys GmbH (D); Cadence GmbH (D).
Contact Point Duration

Joergen Sturm 18 months from 01.11.95

Thesys Gesellschaft fuer Mikroelektronik mbH

Haarbergstr. 61

99097 Erfurt (Germany)
tel: [phone]

fax: [phone]

E-mail: [e-mail]





ESD 22103 DRIVE

Design for Electronic Drive Control
Summary

Special adapted drives require rapid prototyping, short time-to-market, high design security, and high qualified technical support. The intelligent electronic drive control products of port are designed with DSP for control algorithmic and machine safety. In addition, FPGAs are used to connect power stages and measurement systems and for realising fast communication and logic control. To design new improved products, one task is to evaluate a commercially available development tool set and to use it to improve the design efficiency within a design experiment integrating new state of the art FPGAs with new functions into the motion products of port.

Objectives

· The experiences in designing complex motion control products and high speed industrial communication have shown new requirements in the approach to electronic design. The complex planning of work and resources improves the quality assurance system of port .

· The new approach to electronic design is a first step to a linked hard- and software databank for control functions. The start of a new motion controller family will be enabled by using a new development tool set with support of mixed hardware/software design.
· Commercial impacts are expected in various directions; shorter development cycle times, higher quality outputs in electronic system design, predictable results, and re-usability of components for other projects.
· The goal of the project is very important also for other high technology oriented companies especially in the motion control market, e.g. for easy and fast solution of motion control problems with difficult dynamic properties, short time-to-market by rapid prototyping, and volume dependent cost optimisation of the final product.
Participants

port GmbH (D)
Contact Point Duration

Mr. Michael Suess Project Engineer 18 months from 15.04.96

port GmbH

Droyssiger Weg 56

D-06188 Hohenthurm (Germany)
tel.: [phone]

fax : [phone]

E-mail: [e-mail]
EP 22105 PARIS

Usability Optimisation and Productivity Enhancement of the Integrated Layout Tool PARIS
Summary

In order to reduce costs and increase the productivity in integrated circuit and system design, the new design tool PARIS was developed and combined with a technology independent layout module generator for the realisation of complex mixed-signal circuits. PARIS will be evaluated in the course of this project by using it in the design of a sensor ASIC. Major aspects of the evaluation will be the optimisation of the user interface, the enhancement of the module generators as well as the streamlining of technology file generation and administration. Compliance of the tool's interfaces with a number of industry standard data formats will be verified by cross-checking the layout and mask data with renowned manufacturers' database specifications.

Objectives

· Speed up the development time and reduce the risk of the introduction of a new CAD tool by achieving a simple and intuitive, yet powerful and flexible, user interface and software structure.

· Decrease the development cost of ICs by utilising a development tool which is capable of running under a variety of operating systems and hardware platforms, including workstations as well as PCs.
· Feedback from the participating ASIC design companies to the software developers for user driven optimisation of PARIS with respect to the user's experience and requirements.
· Improvement of the adaptability of the software to the user's style as well as better understanding of the designer's philosophy and handling practice.
· Achieve a better market acceptance by cooperation with industrial users and providing a fully evaluated and demonstrated tool in a reference project for potential customers.
Participants__Italtel_SpA._(I)'>Participants___CISS_(A);'>Participants

CISS (A); aiss (D); ASIC (D)
Contact Point Duration

Klaus Jöstl 18 months

CISS - Consulting - Integrierte Schaltungen

und Software GmbH & Co KEG

Grottenhofstrasse 3-7

A-8053 Graz (Austria)
tel.: [phone]

fax: [phone]

E-mail: [e-mail]

EP 22133 SEED

Software/Hardware Exploration: A European Demonstration Project
Summary

The development of an improved design methodology for mixed hardware/software embedded systems with real-time constraints is required for telecom applications. A design flow for this type of application will be developed and tested using a prototype environment developed at COGEFO/CEFRIEL, named TOSCA. This environment allows the user to specify and bind different parts of a design to hardware or software units. A critical control module for telecom applications will be designed exploiting the TOSCA environment, and analyses of hardware and software partitioning will be evaluated. From this design experience, improvements and user requirements will be implemented in the prototype environment. A marketing activity will be activated by the CAD vendor to introduce the design methodology thus identified to other potential customers for possible commercial exploitation.

Objectives

 Design of an improved application in the telecom domain applying the prototype co-design environment TOSCA. A control module of the UT100 public switching exchange system has been selected.

 Improvement of the prototype tool TOSCA exploiting the industrial experience in system design gained with the application.

 Development of a design methodology and an integrated design flow for hardware/software mixed applications, considering in particular the phases of system specification and architectural exploration.

 Dissemination of the results of the project driven by a detailed technology transfer plan, including workshops presentations mainly aimed at SMEs.

 Exploitation of the engineering knowledge of the CAD vendor in order to gain enough confidence to bring the prototype environment eventually to the market.

Participants__Nord-Micro_AG_(D)_Contact_Point_Duration'>Participants__Thomson_CSF_Communications_(F);'>Participants

Italtel SpA. (I); Cogefo (I); Mentor Italia (I).
Contact point Duration

Massimo Bombana 15 months from 01.07.96

Italtel spa

DRSIT-RSC-SM CLTE

Castelletto di Settimo Milanese

20019 Settimo Milanese (MI), (Italy)
tel: [phone]

fax: [phone]

E-mail: [e-mail]

EP 22169 ENPROCO

Enhanced Processor-Based System for Electronic Control Applications
Summary

The demonstration project ENPROCO aims to transfer research knowledge on HW/SW codesign, to small-size companies developing embedded systems based on small 8 to 16 bit microcontrollers. The research prototype HW/SW codesign platform CASTLE, developed at GMD, will be adapted and extended to support the specific requirements of such small and medium sized companies. New tools, such as emulators for the special microcontrollers in use there, will be added to the codesign system if required.

Objectives

· Improve efficiency in electronic system design by the early introduction of novel design tools to an industrial partner.

· Transfer of know-how in design methods and tools to small-sized companies for better productivity and competitiveness.
· Demonstration of a practical gain in design productivity form advanced ESDA tools.
· Development of improved products with a shorter time-to-market.
· Acceleration and support of the adaptation of prototype CAD tools towards viable software products.
· Documentation of added value in system design through the use of novel tools, thereby preparation of their commercialisation.
· Demonstration of a possible leap in productivity to European industries with focus on small and medium sized companies.
Participants

KML Elektronik (D), GMD (D)
Contact Point Duration

Edgar Peter 24 months from 01.04.96

KML Elektronik GmbH

Hertzstrasse 14

D-53844 TROISDORF (Germany)
tel: [phone]

fax: [phone]

E-mail: not available yet, may use [e-mail]





EP 22203 VITALISE

VXI Industrial Test Applications for Liaison with IEEE 1149.1 System Environments
Summary

The “Vitalise” project demonstrates the introduction of a new generation of mixed-signal test solutions and test concepts - combined with boundary scan compliant applications - in the development organisation of a leading mobile communication supplier.

Objectives
· to allow for fast prototyping of new subsystem technologies for embedded applications such as the rapidly evolving PCMCIA applications, Multi-Chip-Modules (MCMs), Systems-on-Chip (mainly for telecom and multimedia applications).
Participants

Thomson CSF Communications (F); microLEX Systems A/S (DK)
Contact Point Duration

Francis Pichon 16 months from 01.07.96

Thomson CSF Communications

Rue du Fosse Blanc 66

BP156
F-92231 GENNEVILLIERS (France)
tel: [phone]

fax: [phone]

E-mail: [e-mail]

EP 22249 ADTV

ASIC Design Transfer Using VHDL
Summary

With ASIC technology being improved every year, ‘old’ manufacturing processes are phased out and chip designs have to be retargetted to new processes. For applications with a low series production volume, the non-recurring costs of gate array redesign add a significant contribution to the product price.

As today cheap FPGAs are available in complexities that were reserved for gate array design some years ago, devices, tools, and methods will be evaluated to transfer from gate array technology to FPGAs for such applications. The tools and methods will further allow a high flexibility in future selection of device types, manufacturers, and technology.
Objectives

 A market survey will be performed to determine which FPGA product family will best suit the model application.

 A market survey will be performed to determine which design tools will allow a maximum of flexibility and independence of a specific manufacturer and/or ASIC/FPGA product family.
 Using one sample design, experience shall be gained how to transfer from a gate level description to a VHDL description for the purpose of portability.
 Evaluating two sets of design tools and two different FPGA product families experience shall be gained on design productivity and efficiency ( design cost, product cost ).
 Design methods and rules will be determined to ease future retargetting activities.
 The retargetted design will be simulated to a confidence level allowing a follow-on activity for production implementation.

Participants

Nord-Micro AG (D)
Contact Point Duration

Rainer Schulze, E2 15 months from 01.04.96

Nord-Micro AG

Victor-Slotosch-Str. 20

D-60388 Frankfurt / Main (Germany)
tel: [phone]

fax: [phone]

E-Mail: [e-mail]
EP 22253 DEMOMAG

Design and modelling improvement of magnetic components for aerospace applications
Summary

Performance and design process of Switched Mode Power Supplies (SMPS) are improved by means of the improvement of the design, modelling and manufacturing process of the power magnetic components. The influence of magnetic components in high frequency DC/DC converters is critical. Furthermore, the performance of HF magnetic components is very dependent on winging strategy and geometry effects, which are not properly calculated and predicted today. The Magnetic Element Modelling Tool (MEMT), based on Finite Element Analysis calculations, is used to generate accurate frequency dependent behavioural models, useful to guarantee adequate performance and save time in the design and development process of the whole SMPS.

Objectives

 Accurate behavioural models, accounting for geometry and frequency dependent effects are obtained for the SMPS magnetic components. Layers position, sensitivity to track and isolation dimensions, etc., will be calculated with the new MEMT tool.

 Improvement of magnetic component performance, because the capability to obtain an accurate model before building the magnetic component and the physical insight by means of the Finite Element Analysis allows component optimisation.

 Improvement of SMPS, because performance of SMPS is highly dependent on magnetic components. Efficiency, stress, size, thermal management, etc, are more accurately calculated since accurate models are available.

 Improvement of design process: allows performance of electrical simulations and to check whether results are as expected before building magnetic component and SMPS.

 Development time reduction: design will not be iterative. Iterations will be done by computer, but not in the construction of the magnetic components.

 Cost reduction: due to the development time reduction and manufacturing cost of low profile PCB transformers, that is lower than hand made transformers when leakage inductance reduction is a must, as in this case.

Participants

ENOSA (E); UPM (E)
Contact points Duration

Carmen Guerra / Julio Cezón Jose A. Cobos 12 months from 01.05.96

ENOSA UPM

Joaquin Rodrigo 11 Jose Gutierrez Abascal 2

28300 Aranjuez, Madrid (España) 28006. Madrid. (España)
tel: [phone] tel: [phone]

fax: [phone] fax: [phone]

E-mail: [e-mail]

EP 22409 EMCLO

EMC Design Methodologies for PCB Layout Optimisation

Summary

The aim of this Demonstration Project is to show the viability of a prototype tool in performing predictive analysis and screening of EMC (Electromagnetic Compatibility) problems on PCB; the extraction, analysis and improvement of critical track configuration and the integration with the design methodology in our company. To prevent EMC compliance from posing a problem at product level, every level of the system from the design of the ground structure, to the selection of ICs and decoupling capacitors, to PCB layout must be considered. EMC problems which cannot be located before the prototype is tested, or, which are ascertained by the service technician at the customer site, create prolonged development cycles, excessive efforts during the testing period and decrease customer confidence due to lack of product quality.

Objectives

 Perform predictive analysis and screening of EMC problems on PCB, the extraction, analysis and improvement of critical track configuration and the integration with the design methodology.

 Component value and layout optimisation.

 Product control at each development phase. With more stringent international EMC regulations on the horizon and shortened development cycle, MMDE cannot afford re-designs due to EMC problems discovered just prior to volume manufacturing.

 Viability of the prototype tool; HDT will cover the EMC market with a unique solution for conducted and radiated emission, a mature prototype proved on a real industrial problem and a tool customised in accordance with final user requirements.

 Reduction of design iterations; measurement reduction: ie measurement to be taken before manufacture.

 Promote the use of the defined methodology through publication of "application notes" with the case study.

Participants

Magneti Marelli Electronic Division, MMDE (I); High Design Technology, HDT (I)
Contact Point Duration

Diego Lasagna 9 months from 01.05.96

Magneti Marelli S.p.A.

Research & Development Design Automation

Corso G. Cesare 328 - 10154 Torino, (Italy)
tel: [phone]

fax: [phone]

E-mail: [e-mail]

EP 22415 GERTRUDE

Printed Circuit Board CAD/CAM data Transfer using EDIF
Summary

GERTRUDE is a Demonstration Project in which high-level electronic data transfer between design systems (CAD) and manufacturing systems (CAM), based on the emerging EDIF Version 4.0.0 data format for PCBs and Multichip Modules (MCMs) will be establsihed and demonstrated. A significant part of the EDIF format has been developed within Europe, supported by Esprit Project ESIP (8370).

Objectives

· Significant reduction in cost for data transfer (20% saving)

· Significant reduction in time to market for PCBs (from 7 days to 5.5 days)
Participants

Nokia Mobile Phones Ltd (UK); Orbotech (B); Redac Systems (UK); University of Manchester (UK)
Contact Point Duration

Dominic Lobo 12 months from 17.06.96
Nokia Mobile Phones (UK) Ltd
Ashwood House, Pembroke Broadway
Camberley,

Surrey, GU15 3XD (United Kingdom)


tel: [phone]

fax: [phone]

E-mail:[e-mail]

EP 22821 OPTISSIMO

Evaluation and Demonstration of the Optical Proximity Correction and Simulation Tool OPTISSIMO
Summary
OPTISSIMO is a newly developed software tool from AISS for optical proximity correction and simulation in IC manufacturing. Optical Proximity Correction is a novel technique which extends the practical resolution limits of existing optical lithography equipment by at least one IC generation. OPC modifies the design data of an IC to correct for the diffraction phenomena encountered when printing close to the limits of the optical tool. OPTISSIMO is able to do this modification on the data volume of a whole chip in a reasonable time with sufficient accuracy for state-of-the-art ICs.
Objectives

· In this project, Siemens Semiconductor validates and demonstrates OPTISSIMO on real IC designs. AISS receives feedback for the simulation accuracy, for optimisation and for better understanding of any restrictions in the practical application of OPC. So AISS can increase the usability and obtain the best functionality for industrial use of OPTISSIMO.

· The output of the project will be a commercially available software tool, that reflects the practical needs of IC manufacturing. Reports will describe the experiences with OPTISSIMO and deliver information about best practice for application.
· For Siemens Semiconductor, this project provides early access to a key technology developed according to the actual needs by an European software company. This opens the possibility for further shrinks of IC design geometries without the investment in next generation lithography tools. For AISS, the cooperation with Siemens provides application results in an industrial environment and a capable and competent partner to guarantee the commercial and technical success of the software package.
· The results of the project will be published at international lithography and design conferences, as well as in reports to the EC.
Participants

Siemens AG (D)
Contact Point Duration

Wilhelm Maurer 15 months from 01.11.96

Siemens Semiconductor Group HL ST TE M3

Otto-Hahn-Riung 6

D-81479 MUNICH (Germany)
tel: [phone]

fax: [phone]

E-mail: wilhelm.maurer.hl.ostc.siemens.de

EP 22979 YETI

Yield simulation and enhancement Tool YETI
Summary

For the integration of electronic systems in telecommunications, automobiles and consumer electronics the demands with respect to the performance and time-to-market are increasing rapidly. Thus the efficient control of the concurrent engineering processes design, layout and production line performance is of essential importance for the optimisation of the overall function of integrated circuits.

Objectives

· A very important part of the design flow is the design verification to improve the yield. The design and the layout have to be examined not only in the view of minimisation of silicon area used or high speed of the circuit, but also with respect to manufacturability. If we want to generate such robust designs, the existence of parameter variations resulting from unintentional variations in the process parameters must be accounted for.

· A second issue of design verification is to find weaknesses in the layout. This is especially important for digital CMOS circuits as for a stable production line the yield is limited by functional yield losses (not parametric yield losses). Spot defects occurring unavoidably during the production process limit the achievable yield.
· AISS Gmbh has developed YETI, a new yield estimation and optimisation tool which assimilates all experience and know-how from research to date. The basis of YETI is the computation of critical areas on the layout level especially for shorts between conducting regions. It enables the choice of different defect models, simulation of process induced layout deformations as observed in manufacturing like over/under etching, rounding of corners, optical proximity effect simulation and both numerical and visual output or results.
· The evaluation and investigation of YETI by Siemens under industrial conditions for layout characterisation with respect to defect-related yield, compatible with the existing design flow, is the goal of this project. For selected circuits especially sensitive to failure modes caused by spot defects, the new tool will be applied to show how the yield can be calculated in advance and how the layout can be optimised for higher yield.
Participants

Siemens AG (D)
Contact Point Duration

Susanne Griep 12 months from 01.11.96

Siemens Corporate Research and Development

Otto-Hahn-Ring 6

D-81739 MUNICH (Germany)
tel: [phone]

fax: [phone]

E-mail: [e-mail]

EP 23037 FORSITE

FORMAT Software in an Industrial Environment
Summary

This Demonstration Project will integrate a prototype tool using symbolic timing diagrams as a rigorous graphical specification language into an existing commercial tool (CheckOff). The improved tool will be evaluated through development of a PCI to Memory I/O ASIC. The new tool will allow designers to validate the correctness of an implementation against a design specification without the cost and time needed for traditional simulation.

Objectives

· Reduction of 5 to 15% of engineering costs due to reduced logic simulation.

· Where use of formal methods prevents a redesign, additional cost savings of up to 30% are expected.
· Increased value of CheckOff-M software tool product by 20%.