Ep optima synopsis

Participants

Siemens AG (D); Abstract Hardware Ltd (UK); OFFIS (D)
Contact Point Duration

Dieter Werth 12 months from 01.11.96
Siemens AG (AUT GT 23)
Gleiwitzer Str. 555
D-90327 Nürnberg (Germany)
tel: [phone]

fax: [phone]

E-mail:[e-mail]

EP 24097 PROSAFE

Software-supported Prototyping and Real-time Implementation of Intelligent Multisensor-based Safety Control Systems
Summary

Since classical business areas show saturation effects, the proposed project is expected to strengthen Alcatel’s activities in the development of new strategic market opportunities, such as intelligent information processing products. Alcatel SEL’s interest in participating is related to the introduction of novel design methods for Artificial Neural Network and Fuzzy Logic-based information processing systems and has therefore a strategic dimension. Hence, a next generation prototype software tool will be used for rapid prototyping and fast realisation of a Neural Network-based product for the evolving market of security systems and services.

Objectives

· In the proposed project, the design of an electronic surveillance system for the detection of human intruders into protected areas on the basis of multi-sensor input signals will be demonstrated. Using already simulated neural network-based algorithms, the focus of the proposed Demonstration Project will be on integrated system realisation in one single software environment for all design steps. These include graphical input of the neural network topology, source and DSP program development supported by the tool’s automatic code generation features, system evaluation on the same standardised PC-based platform, and final evaluation of the design process using the DSP-based target prototype system. Expected impacts will be on the minimisation of design costs and time-to-market as compared to traditional design methods.

· Furthermore, easy maintenance and further improvements of the target system is expected to be supported by future releases of the prototype Design tool. One example will be an improved functionality by tool-supported integration of Fuzzy Concepts into the next version of the surveillance system.
Participants__Alcatel_(D)_Contact_Point_Duration'>Participants

Alcatel (D)
Contact Point Duration

Michael Trompf 13 months from 01.12.96

ALCATEL ZFZ/SC

Holderäckerstrasse 35

D-70499 STUTTGART (Germany)
tel: [phone]

fax: [phone]

E-mail: [e-mail]
EP 24268 TACTIC

Test Applications concerted for Telecom Industry Challenges

Summary

TACTIC introduces a new generation of mixed-signal test verification solutions to the Nokia mobile communication division (NMP). This will allow fast verification of new mixed-signal applications by emulating critical analogue functionality of a given mixed-signal IC design and hence allow debugging of test and verification programs before the actual prototype chip is available.

Objectives

· One main objective is to reduce the verification and debugging time associated with new mixed-signal prototype chips by 1-2 months to improve the time-to-market in the fast evolving mobile telephone business segment.

· Another important aim is to reduce the entire job of creating a test and verification solution for new complex mixed-signal components. This will make the program development effort significantly more efficient and allow the user company to handle even more complex solutions within a reasonable resource.
· It is planned to show clear improvement with respect to the user’s existing techniques in verification of mixed-signal applications. This will include reductions in test cost (e.g. improved throughput, lower total test costs, etc.). Part of the strategy is also to improve accuracy and measurement techniques such as multitone testing and other DSP based testing methods. Improved transfer of results from the user’s mixed-signal design environment, as well as ease-of-use is an area where significant achievements can be gained. The openness of the system approach taken, promise well for future upgrade, and may prove a major advantage for wider applications.
· It is planned to make known the results to other industries, not least those of the telecommunication sector. The user and the tool provider will make efforts to have the major results presented at key international events such as the European Design & Test Conference and the International Test Conference. The tool provider will also through sales efforts and dedicated seminars, be involved in dissemination. Seminars as part of the FUSE program could bring the results to a broad range of beneficiaries.
Participants__MLS_Firmware_SA_(GR)_Contact_Point_Duration'>Participants__Lucas_Applied_Technology_Ltd_(UK);'>Participants

Nokia Mobile Phones (SF)
Contact Point Duration

Tapio Koivukangas 16 months from 01.01.97

Nokia Mobile Phones - IC-Technology

Elektronilikkatie 10

FIN-90571 OULU (Finland)
tel: [phone]

fax: [phone]

E-mail: [e-mail]

EP 20378 FASTTRACC

Formal Analysis and Specification Tools to Realise Adaptive Cruise Control
Summary

FASTTRACC is an Application Experiment in which Lucas will undertake the design of a safety critical automotive component using the formal methodology and tools from AHL. Safety-critical systems are becoming more complex and more common-place. There are as yet few tools which address the issues of ensuring that a specification is both well-founded and implementable. One tool which has recently appeared on the market and which addresses the issues of safety-critical design is the LAMBDA tool from AHL. It is likely that as complexity continues to rise, standards authorities (e.g. Def Stan 00-55) will mandate the use of tools such as LAMBDA as best practice for the design of safety-critical systems.

Objectives

· To assess the applicability of using mathematically formal techniques (LAMBDA) in the design of an adaptive cruise control system for an automobile.

· To improve the design efficiency in terms of shorter design cycle and higher design integrity.
· To allow re-usable designs through use of design history feature.
· To disseminate the results throughout the community.
Participants__ECON_Industries_SA_(GR)_Contact_Point_Duration'>Participants

Lucas Applied Technology Ltd (UK); Abstract hardware ltd (UK)
Contact Point Duration

Karen Hale 12 months from 01.01.96

Lucas Advanced Engineering Centre

Dog Kennel Lane, Shirley,

SOLIHULL B90 4JJ, (United Kingdom)
tel: [phone]

fax: [phone]

E-mail: [e-mail]

EP 20385 MLS

Design of an Interface ASIC for RISC systems using a VHDL based "Independent" Environment
Summary

This Application Experiment has as its main objectives the utilisation of VHDL, the use of an "Independent" Environment and the adoption of an advanced design methodology in order to improve the standard of design practice currently used by MLS Firmware S.A (OrCAD & ViewLogic EDA Tools).

The Application Experiment will focus on the design of an advanced interface ASIC for the R4000 RISC family of IDT microprocessors that is used in high-performance embedded control systems i.e. fast telecommunications switching, high-speed networking (ATM switches) etc. The product will be tested with advanced prototype testing methods. The ASIC design will be carried out by MLS engineers with the support of INTRACOM engineers to ensure that the end-user learns sufficiently to repeat the process in the future without support.
Objectives

· The adoption of an advanced design methodology with the use of VHDL and the design of an interface ASIC for the R4000 RISC family of IDT microprocessors. MLS plans to design this ASIC in collaboration with the Centre of Microelectronics of INTRACOM (CEM). CEM will provide the advanced design practice, the training of MLS engineers, the final Mentor Graphics platform environment and will do the final technology choice as well as supporting the implementation of the ASIC.

· To strengthen MLS' position in the embedded control systems market and in the prototype development work.
· To disseminate the results of this Application Experiment on a European-wide scale.
Participants__Intracom_SA_(GR)_Contact_Point_Duration'>Participants

MLS Firmware SA (GR)
Contact Point Duration

Dr Nikos Zissis 15 months from 01.10.95

MLS Firmware S.A.

Alex Papanastasiou St. 34
GR-54639 THESSALONIKI (Greece)
tel: [phone]

fax: [phone]

E-mail: [e-mail]

EP 20388 SYNC

High level synthesis of a remote I/O for a Numerical Control system
Summary

The object of this Application Experiment is a full and practical test for assessing the actual advantages to be obtained by a small enterprise in using a modern (and very expensive) automated synthesis tool (SYNOPSYS) for the design of electronic systems based on full-programmable devices. The experiment is based on the complete design of a family of modular units for actuating a variety of I/O devices interconnected with a fibre optic link.

Objectives

· Introduce a new and up-to-date design technology which, to a previous analysis, did not appear to be economical for a small enterprise.

 Compare the cost of design of electronic modules using traditional methods and a high level automated system.
· Improve the quality of electronic design with the use of automatic simulation and timing analysis.
· Increase the competitive position of the company by the reduction of time-to-market of new products and more modular structures in the products.
 Analyse the time required to prepare all necessary tools (hardware and software) to make the board testable on automatic testing machines in production.
· Increase the productivity of designers allowing them to concentrate on system functionality described as an algorithm rather than in terms of circuits and gates.
Participants__Bizerba_GmbH__Co._KG_(D)_Contact_Point_Duration'>Participants

SELCA SpA (I); Politecnico di Torino (I).
Contact Point Duration

Piero Pomella 15 months from 01.10.95

Selca S.p.A

Corso Vercelli 123

IVREA 10015 (Italia)
tel: [phone]

fax: [phone]

E-mail: [e-mail]
EP 20413 HARCODA

Hardware realisation of communication coding algorithm
Summary

An innovative design and development environment is to be introduced using advanced EDA software tools. The new design process solution will be used for the development of an electronic system for use in data communication for the purpose of data security and integrity. The heart of the system will be an ASIC designed to realise a coding algorithm. Benefits of using advanced ESD tools will be disseminated to specific industrial sectors.

Objectives

· Introduction of an evolutionary system development cycle based on concurrent engineering principles, replacing the existing traditional electronics design chain.

· Minimising development time through the use of the new design methodology will reduce product cost and improve quality.
· Demonstration of the improvement in the design practice through the design of a high complexity ASIC.
· Targeted dissemination of activities to the Greek Electronics Industry.
Participants

ECON Industries SA (GR)
Contact Point Duration

John Spanoudakis 18 months from 01.10.95

ECON INDUSTRIES S.A.

P.O. Box 60, 19003 Markopoulo, (Greece)
tel: [phone]

fax: [phone]

E-mail: [e-mail]
EP 20455 QESDI

Quantification of ESD Economic Impact for SMEs
Summary

This Application Experiment focuses on the use of advanced CAD tools. It is concerned with the design of an advanced model of an electronic cash register, a hot-line product of M&S HOURDAKIS SA, a Greek SME electronics manufacturer. The objectives of the project are to improve design efficiency through the application of the new tools to the design of an improved product.

Objectives

· To achieve a higher degree of integration.

· To achieve a higher degree of manufacturability.
· To achieve a higher degree of reliability of designs
· To disseminate the results throughout the community.
Participants

M&S Hourdakis SA (GR)
Contact Point Duration

Constantine Mouzakis 11 months from 01.01.96

M&S HOURDAKIS SA

Industrial Area Koropi

Nomos ATTIKIS GR-19400 KOROPI (Greece)
tel: [phone]

fax: [phone]

E-mail: [e-mail]

EP 20509 STAY ON

ASIC Solution for Dedicated TV Camera
Summary

A dedicated, compact and cost-effective TV camera is to be designed for use in an Optical Character Recognition (OCR) subsystem as well as in a remote surveillance system. It must therefore be capable of performing pattern recognition and motion detection functions. ASIC technology has been selected to achieve the best price-to-performance ratio. Most of the image analysis functions are performed by the ASIC now in development and the complete system just requires few very low cost components other than the microprogrammable ASIC itself to do the required job.

Objectives

· That the OCR under development can readily perform static image acquisition; it is simple and reliable and its production price can be very competitive in comparison with already available similar devices.

· That the ASIC itself can be profitably used in other planned products that require image analysis, such as a surveillance TV camera or a digital remote TV camera connected to the control monitor via a telephone line.
· The acquired microelectronic experience is to be transferred to other products, leading to enhanced performance and substantial savings in production cost.
Participants

Metalplex SpA (I); Edelpro SRL (I).
Contact Point Duration

Cosimo La Ragione 12 months from 01.011.95

Metalplex SpA
tel: [phone]

EP 20548 SEM-A-HDL

Smart Energy Meter design using novel CAD tools that support Analogue HDL modeling techniques
Summary

The aim of SEM-A-HDL is the comparison of the conventional way of implementing the Smart Electronic Energy Meter with the outcome of the Application Experiment: the same device design completed (at the behaviour level) using A-HDL based methodology. The most important goal is the exploitation of novel modelling techniques based on A-HDL (extension of VHDL for the analogue case) through modern CAD tools. The experiences accumulated during the development of the Smart Energy Meter will be valuable both for the user company for all their future mixed-signal products, as well as for all interested SMEs and Design Houses including the subcontractor. A parallel goal (supported by company resources) is the development of a Smart Electronic Energy Meter, an efficient solution that overcomes the constraints of the old Ferraris-type electricity energy-meter.

Objectives

 To efficiently design a Smart Electronic Energy Meter device which will overcome the constraints of the old Ferraris-type one, and will provide advanced services like fraud detection, multi-tariff capabilities, two alternative ways of communication for the transmission of billing and status information etc.

 To introduce and exploit novel modelling techniques based on A-HDL in mixed designs .

 To demonstrate through efficient execution of the specific experiment the improvements that could be achieved in mixed hardware designs by employing the project’s emerging techniques and tools with respect to existing ones, in terms of better modelling, more reliable design procedures, reduced errors and redesign cycles and shorter time-to-market.

 To disseminate the experiences and lessons learned, through the execution of the specific experiment, in digital/analogue designs to SMEs and other interested bodies.
Participants

Intracom SA (GR)
Contact Point Duration

Dimitris Dervenis 18 months from 01.11.95

INTRACOM S.A.

19,5 km Markopoulou Ave

19002, Peania, Attika (Greece)
tel: [phone]

fax: [phone]

E-mail: [e-mail]

EP 20605 PCASIC

Personal Computer tools for the design of Application Specific Integrated Circuits
Summary

PCASIC is an Application Experiment which aims to provide Fint with experience with state-of-the-art design methods in digital microelectronics and establish a safer design route with minimum risk of reruns on developed ASIC designs.

Objectives

· To establish a Best Practice design methodology within Fint in order to provide better products and to bring these products quicker to the market with a higher degree of success.

· To establish a design practice using VHDL. Evaluation of use of VHDL as a suitable tool for a small size company with minimal experience in high level description of design. The design time and efficiency of the design will be compared with schematic design tools.
· It is further aimed to establish a design practice using FPGA as a development and test tool before the final implementation is done in ASIC. The design will be functionally tested using FPGAs. The library-modules are different for the two technologies and the intention is to work in different design environments in the two cases.
· The main results expected are tools and experience in using such tools that allow Fint to develop products with a higher degree of functionality with a faster and safer design time. Experience will be acquired in design time and in design efficiency in terms of design errors and how this is affected by the design tools.
· These experiences will be shared with other companies through the Norwegian IT Industries Technological Fora and through presentation at relevant workshops such as the CAD Forum.
Participants

Fieldbus International AS (N); SINTEF (N)
Contact Point Duration

Jan Roar Remøy 16 months from 01.10.95

Fieldbus International AS

P.Box 107 Blindern

0314 Oslo (Norway)
tel: + 47 22 06 73 19

fax: + 47 22 06 73 20

E-mail: [e-mail]

EP 20702 EESD

Enhancement of Electronic System Design by EMC Adviser System
Summary

The EESD project aims to improve the HWDC (hardware design cycle) by integrating a method of handling EMC (Electromagnetic Compatibility) problems as early as possible in the design and implementation phases. For the improvement of design efficiency, the proposed method deals with rule-based EMC evaluation. Bizerba expects to integrate the commercial EMC Adviser tool into the HWDC to avoid any costly, time-consuming and EMC-induced redesigns of the products. This is an essential prerequisite for expediently translating the developments into products ready for the market. These expected benefits result in a significant competitive advantage, especially in relation to Far East and South East Asian producers.

Objectives

 Higher hardware quality

 Quantifiable EMC quality control: A design integrity meter is used to graphically show if the hardware system design conforms with EMC requirements.
 Reduced development cycles (= costs) and increased competitive advantages: Backed up by EESD procedure, the new finished products can be launched and placed on the market much faster, having a positive effect on customer response and product acceptance.
 Easy handling of EMC Adviser tool: The handling of the tool is easy to understand, the more so, as a rule-based Expert System is used in lieu of customary simulators.
 Enhanced motivation and increasing productivity/profitability: As the planning of project sequences improves and results are fairly predicted, the design engineer and associated staff become more highly motivated. Iterations after the testing phase are avoided.
Participants

Bizerba GmbH & Co. KG (D)
Contact Point Duration

Werner Sauter 13 months from 01.09.95

Bizerba GmbH & Co. KG

Department TE-BS-H, Post box 10 01 64

72301 Balingen (Germany)
tel: [phone]

fax: [phone]

E-mail: [e-mail]

EP 20883 PODSIM

ISDN simulator pod supporting multiple S_2M links
Summary

This Application Experiment concerns the redesign of an ISDN pod for advanced test equipment, to support multiple S_2M links. V5.2 systems can use up to 16 S_2M interfaces between the Access Network and Local Exchange, and a simulator must be able to handle this in order to test these systems in their maximum configuration. Signalling system number 7 exchanges share their message load over several links, and over a maximum of 4 channels within each link. This is beyond the current capabilities of any test system thus making a qualitative assessment impossible.

Objectives

The increased demands of a primary rate system in terms of both processing power and I/O bandwidth will require a far more sophisticated design tool than was used for the original system. The new design environment should offer the following advantages :

 integrated solution covering all aspects of the design process from circuit/schematic entry and analogue and digital simulation/analysis

 large component libraries and the ability to import standard descriptions (e.g. VHDL)

 integrated ASIC design capabilities

 support for future enhancements and technological changes

The use of modern design tools and methods will have a direct impact on the cost and quality of the electronic products designed and developed by the company as well as in other factors (time-to-market) which determine company's place in the market. The direct benefits expected could be summarised in cost reduction, improved product quality and shorter time-to-market.
Participants

Skelton GmbH (D), ITC SA (GR)
Contact Point Duration

Grigoris Doumenis 18 months from 01.10.95

SKELTON GmbH

Mitltlerer Pfad 26

70499 Stuttgart (Germany)
tel: [phone]

fax: [phone]

EP 22106 PLUTO

Reduced Design Time using PLUTO Demonstrator Vehicle
Summary

PLUTO is an ESD Application Experiment in which Toucan Technology Ltd will introduce new design tools into their ASIC development process. The key commercial impact will be the development of a quicker and more cost effective development process that will enable the delivery of competitive products in a timely manner.

Objectives

The overall goal of the Application Experiment is to reduce the design time for ASIC based products by 20%.

Measurable improvment is expected in the following design process metrics:

• 
  Overall development time
  
• 
  Overall documentation time
  
• 
  RTL and Gate level simulation time
  
• 
  Number of test cases
  
• 
  Gate/RTL test coverage ratio