Ep optima synopsis

Participants

SIDSA (E); Mikron GmbH (D); Warwick Microsystems (UK); Jofemar (E); Universitat Politecnica de Cataluña (E); AICIA (E)
Contact Point Duration

Dr. José Maria Insenser 36 months from 01.01.96

SIDSA

Parque Tecnológico de Madrid, c/ Isaac Newton 1
28760 Tres Cantos, Madrid (Spain)
tel: [phone]

fax: [phone]

E-mail: [e-mail]

EP 21812 AMADEUS

Analogue modelling and design using a symbolic environment
Summary

An interactive circuit design environment will be provided combining advanced symbolic, numerical and graphical techniques that allow the modelling, characterisation and design of analogue circuits. Symbolic techniques will further be explored in tolerance analysis and design centering.

The environment will be developed for exploitation as a commercial CAD tool. An AMADEUS interest group will be established to involve potential external users in definition of requirements and assessment of results.
Objectives

· Available algorithms for the symbolic analysis of linear circuits will be made more robust, gaps will be closed and the application range will be widened. A first product release for linear circuit analysis is planned at the project midterm.

· Non-linear problems like DC large-signal behaviour as well as modelling approaches will be tackled in the second half of the project.
· Furthermore, methods of application will be developed, and application to product design will be demonstrated. Commercial figures will be provided to show benefit and return-on-investment to users.
Participants

Robert Bosch GmbH (D); SGS-Thomson Microelectronics (F); Anacad EES (D); CNM Sevilla (E); KU Leuven (B).
Contact Point Duration

Claus Baumgartner 48 months from 01.03.96

Robert Bosch GmbH

P.O. Box 1342

D-72703 Reutlingen (Germany)
tel: [phone]

fax: [phone]

E-mail: [e-mail]

EP 22797 SEED

Supplier Evaluation and Exploitation of DELPHI
Summary

The thermal precision needed to design out the functional and reliability failures that can result from component overheating requires accurate, validated thermal models of the critical electronic parts used in the design. The DELPHI project (ESPRIT 9197) has therefore developed a technology for the characterisation of the thermal behaviour of single chip packages.

In the SEED project three electronic component manufacturers (Philips Semiconductors, Siemens and SGS Thomson) will evaluate this technology. The results will be disseminated on a wider scale, and steps will be initiated for the industrial adoption of the new methodology.
The co-ordinating partner Flomerics is an SME tool vendor that develops and markets software (FLOTHERM) for thermal analysis at package-, board- and system-level.
Objectives

· Mathematical Reduction techniques will be evaluated, i.e. methods for generating ‘compact’ thermal resistor networks by mathematical reduction of a ‘detailed’ finite-element or finite-volume thermal model of the part.

· The ‘detailed’ thermal models are itself experimentally validated by the following methods for measuring the junction temperature of a chip package under well-defined boundary conditions:

- Double Cold Plate Method - a measuring system where the part is clamped between two temperature-controlled cold plates.

- Submerged Double Jet Impingement Method - a measuring system where the part is immersed in a fluid and subjected, on both sides, to impinging fluid jet streams.
· The ultimate beneficiaries of SEED are the equipment manufacturers, who can build more reliable electronic equipment if the component manufacturers supply validated thermal models of their parts.
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Flomerics Limited (UK); Philips Semiconductor (NL); SGS-Thomson (I); Siemens Semiconductor (D); Alcatel Bell (B); Thomson-CSF RCM (F).
Contact Point Duration

John Parry 36 months from 01.03.97

Flomerics Limited

81 Bridge Road

Hampton Court, KT8 9HH (United Kingdom)
tel: [phone]

fax: [phone]

E-mail: [e-mail]

EP 23643 ESDEM

ESD Protection Design Methodology
Summary

A design methodology will be developed that employs device and circuit simulators to devise and to optimize integrated circuit ESD protection structures. The design metho­dology for production will change from the current largely-empirical approach, based on extensive destructive testing, to TCAD-guided critical parameter evaluation, validated by a relatively small number of specific high current measurements.

Objectives

· To gain insight in ESD-problems and to investigate possible design options for a well-established smart power technology, as well as design and processing options for an advanced VSLI technology with the aim of a robust ESD performance;

· To investigate and optimize the behaviour of protection devices under different ESD stress models, including Human-Body Model and Charged Device Model,
· To provide basic physical models that are still lacking and that are relevant for ESD-modelling,
· To develop respective TCAD code and make it commercially available.
Participants

R. Bosch GmbH (D); SGS-Thomson Microelectronics (I); IMEC (B); University of Bologna (I); ISE AG, (CH); Federal Institute of Technology Zurich (CH).
Contact Point Duration

Wolfgang Wilkening 24 months from 01.01.97

Robert Bosch GmbH

P.O. Box 1342

D-72703 Reutlingen, (Germany)
tel: [phone]

fax: [phone]

E-mail: [e-mail]


Enhancement of Technology and Manufacturing Base

EP 20485 TIBIA II

Technology Initiative in BICMOS for Applications
Summary

The objective of this project is to satisfy the systems needs of the electronic equipment markets for Bipolar and BICMOS ICs. This will be achieved by developing and establishing BICMOS and Bipolar technologies at the 0.5 micron generation together with the design and CAD expertise to exploit these bipolar technologies. This project will be focused on three subprojects: demonstrators, process assembly and process support.

Objectives

· Initial release of 0.5 micron BICMOS processes (4Q1996).

· Verified and updated design rules.
· Model parameters available for simulations of the designs.
· List of available options in the process: resistors, capacitors, etc.
· Minimum and maximum range of typically achieved parameters describing the electrical behaviour of the transistors.
· Key library cells available.
Results (status December 1996)

• 
  Demonstrator IC’s have been successfully produced in 0.5 micron BICMOS processes
  Results are according to expectations mentioned in the project plan for TIBIA II.
  
  
  
• 
  All partners reached the milestone : Initial release for design
  
  
  
• 
  Co-operation has been especially successful on the emitter-base module
  
  

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Philips SC (NL); Siemens (D); SGS Thomson (F); GEC Plessey (E); Matra-MHS (F); Alcatel Mietec (B); Philips CE (NL); Semiconductores (E); EZM Villach (A); Athens Univ. (GR); EPFL (CH); Telefonica (E); Alcatel SEL (D); Pavia Univ. (I); IMEC (B).

Contact Point Duration

Fokke Postma 15 months from 01.10.95

Philips Semiconductors

Gerstweg 2

6534 AE Nijmegen (The Netherlands)
tel: [phone]

fax: [phone]

E-mail: [e-mail]

EP 20763 SHAPE

Sub HAlf micron cmos Process for European users
Summary

SHAPE is concerned with development of the next generation of 0.35 micron CMOS logic technology. The new technology will be demonstrated by processing innovative VLSI circuits designed in cooperation with major European end-users. The project contains a first phase aiming at implementation and characterisation of process steps, followed by integration of a full CMOS process, targeting the most advanced performances needed by the semiconductor market. At a very early stage, design rules and processing capabilities will be offered to selected users in order to allow advanced system developments in Europe. The developments provide the opportunity for a close and focused cooperation among European semiconductor companies, electronic equipment manufacturers and research institutes to establish in Europe, within a competitive time frame, an early sub-half-micron processing and design capability.

Objectives

· Availability of prototype processing capability in industrial pilot lines by 1996 of a true 0.35 micron CMOS, 3-4 metal, 3.3V process based on the next generation of lithographic tools offering process capability for complex products requiring high density of integration (10K gates/mm²) and high performances (> 0.5 mA/micron for NMOS and > 0.25 mA/micron for PMOS) with reduced power consumption.

· Process specifications and target design rules will be agreed with major end-users with reference to key applications.

· The 0.35 micron base process will be designed to provide also the base-line for further process developments such as analogue addressing specific markets and for an extension later to BICMOS.

Participants

SGS-Thomson (F), Philips SC (Nl), Siemens SC (D), Alcatel-Mietec (B), GEC-Plessey (UK), Matra-MHS (F), AMS (A), Bull (F), Matra-Communication (F), Alcatel-Bell (B).
Contact Point Duration

M. Montier 16 months from 01.09.95

SGS - Thomson Microelectronics

Rue Jean Monnet BP16

38921 Crolles, (France)
tel: [phone]

fax: [phone]

E-mail: [e-mail]

EP 21752 ADEQUAT+

Advanced developments for CMOS for
0.25 micron and below

Summary

The priorities of the European semiconductor industry will be supported through the assessment of key options for advanced CMOS process modules. The project is in phase with the most advanced world-wide efforts currently addressing 0.18 m device architectures and defining 0.25 m interconnect schemes. Target device specifications and lay-out rules for these technological modules have been defined in close interaction with industrial representatives. The results will be assessed and later exploited by the industrial partners in order to reduce their development costs (maximising the utilisation and minimising the risk). The 0.25 m CMOS front-end process modules developed in ADEQUAT-2 (EP 8002) have been modified for low-voltage applications.

Progress and results

• Back-end processing steps and modules for 0.25 m CMOS were developed by 4Q96.

• The implications of using a low supply voltage (0.9 -1.2 V) for 0.25 m CMOS have been assessed through the fabrication of specific test circuits and measurement data will be available by 1Q97.
• Based upon the work of the NOVA-project (E 9159) concepts for 0.18 m CMOS front-end modules are investigated through the fabrication and testing of NMOST and PMOST devices. A lateral isolation module for 0.18 m CMOS will be developed by 1Q97.
• Various techniques were tested for the extension of 248 nm DUV lithography and the feasibility of 0.18 m CMOS front-end patterning has been demonstrated.
• Insight has been provided in the key process parameters affecting device performance and reliability. Benchmarking with respect to competitive results obtained world-wide has been performed.
Participants

IMEC (B); DIMES (NL); FhG (D); GPS (UK); GRESSI (F); Philips (NL); SGS Thomson (F); Siemens (D); CNRS-Univ.Nantes (F); GCIS-LAAS (F); NCSR Demokritos (GR); NMRC (IRL); SGS Thomson (I); TU Vienna (A); Univ. Bologna (I); Univ. Warwick (UK); Univ.York (UK).
Contact Point Duration

Roger De Keersmaecker 15 months from 01.12.95

IMEC vzw

Kapeldreef 75

3001 LEUVEN (Belgium)
tel: [phone]

fax: [phone]

E-mail: [e-mail]

EP 23806 ULTRA

ULsi mosT Research Activity (ULTRA)
Summary

This project is an exploratory work on advanced MOSFET architectures suitable for the 0.13 micron CMOS generation. Technically speaking, this project focuses on the optimisation of the device architecture (e.g. Ground Plane), the emerging new materials (e.g. SiGe, TiN, Ta₂O₅, etc.) and the evaluation of various technological solutions against the end-user defined specifications. The project is divided into four workpackages: Channel Engineering, Gate Engineering, S/D Engineering and Device Specifications.

Objectives

• 
  to perform exploratory work on new device architectures suitable for the 0.13 micron CMOS generation
  
• 
  to consider the introduction of new materials in a standard CMOS process flow
  
• 
  to compare the various technological solutions against the target specifications
  

Participants

SGS-Thomson Microelectronics (F), Siemens (D), Philips (NL), IMEC (B) GRESSI (F)
Contact Point Duration

Dr. Constantin Papadas 24 months from 01.01.1997

Central R&D Technology

SGS-Thomson Microelectronics

850 rue Jean Monnet

BP 16

38921 Crolles Cedex (France)

tel: [phone] (also voice mail)

fax: [phone]

e-mail: [e-mail]

EP 24115 ACE

Advanced CMOS for Europe
Summary

ACE aims at developing Front-end and Back-end process steps and modules for 0.18µm CMOS logic. The workplan is strongly application-driven addressing two generic market segments : high performance and low power applications. The first results of a process validation module for device modules will be available at the end of 97. This will allow processing of first 0.18µm silicon in 1998. First results for the interconnects test structures will be available by 3Q98. The timing of project is in line both with the most advanced world-wide competition (well ahead of the 1994 SIA roadmap) and with the advanced European industrial roadmaps. The concurrent development of Front-end and Back-end modules for the same generation will allow the assessment and optimization of the impact of Back-end process steps on device characteristics and the fabrication of relevant test circuits with critical dimensions of 0.18µm.

The project relies on inputs from the feasibility studes and early development work done within the ADEQUAT+ project on lithography and device architectures for 0.18µm CMOS. It will establish links with downstream projects on process development and with upstream innovative projects on lithography (such as ELLIPSE) and other advanced projects on process and device architectures (such as ULTRA for Front-end and DAMASCENE for interconnects).
Objectives

 To develop the patterning techniques (lithograhy and etching) required for fabrication of 0.18µm CMOS devices and based on 248 nm optical lithography

 To fabricate high performance 0.18µm CMOS devices

 To develop process steps and modules for multilevel metallisation architectures of up to 5 to 6 levels of metal for 0.18µm CMOS technologies

 To validate appropriate developed modules by industrial partners
Participants

IMEC (B); DIMES (NL); FhG ISiT/IIS-B (D); GPS (UK); GRESSI (F); PHILIPS (NL); SIEMENS (D); SGS-THOMSON (F); NMRC (IRL)
Contact Point Duration

H.E. MAES 21 months from 01.03.97

IMEC

Kapeldreef 75

B-3001 Leuven (Belgium)
Tel: [phone]

Fax: [phone]

e-mail : [e-mail]

EP 25220 DAMASCENE

DAMASCENE ARCHITECTURE FOR MULTILEVEL INTERCONNECTIONS

Summary

Circuit performance is becoming dramatically limited by the interconnection.

The resulting demand on interconnect technology requires the exploitation of all development possibilities: materials, basic processes, interconnect architecture and design.

Driven and lead by industry, this project proposes, in a top-down approach from product needs to technology choices, investigation of advanced alternative materials and architecture for interconnection in subquarter-micron technology.

The objective is to achieve significant improvement on interconnection reliability and cost, high signal propagation speed, low power consumption and crosstalk between the nearest interconnection lines.

Innovative solutions for interconnection will be carried out by simultaneous consideration of:

• 
  DAMASCENE architecture in order to achieve simpler interconnect fabrication, better yield and higher density of integration,
  
• 
  Low resistivity COPPER for metallisation with improvement in electromigration and stressmigration,
  
• 
  Low permittivity polymers as dielectrics.
  

Objectives

The final project target is to bring the European expertise up to international level in:

• 
  Manufacturable deposition and patterning for Cu and Al lines and vias in Damascene architecture:
  

Choice of architecture,

Al and Cu deposition process (PVD, CVD, electroplating and electroless),

Al and Cu Chemical Mechanical Polishing (C.M.P.).

• 
  Manufacturable deposition and patterning processes for advanced dielectric, materials in Damascene architecture:
  

Integration of silicon-based low k dielectrics,

Studies of carbon-based polymer dielectrics.

• 
  Integration feasability for these materials and processes in vias and lines Damascene interconnect structures.
  

Participants

SGS-Thomson Microelectronics (F); Siemens (B); Philips (Nl); IMEC (B); GRESSI (F); TU-C (B); NMRC (Irl).
Contact Point Duration

Mr Pierre Bichon 18 months from 09.09.97

SGS-THOMSON MICROELECTRONICS

Central R&D – Joint Program ST/GRESSI

CEA/DTA-LETI – CEA/Grenoble – 17, rue des Martyrs

F -38054 GRENOBLE CEDEX 9 (France)
Tel: [phone]

Fax: [phone]

Email: [e-mail] or [e-mail]

EP 21760 ELLIPSE

Excimer Laser Lithography Project

for Sub-Quarter Micron Era
Summary

The project links leading European materials and equipment suppliers and research institutes in the area of advanced lithography, being the first phase of a combined European effort to provide 193 nm lithography tools and resists for the Gigabit DRAM technology generations, i.e. for 0.18 and 0.12 micron feature sizes. The two main workpackages will focus on production exposure tool design and predevelopment and on a litho cell for 193 nm process development. The ultimate goal is to make available a European optical exposure tool and resist processes compatible with 0.18/0.12 micron manufacturing requirements by the year 2000.

Objectives

· Provision of concepts for a 193 nm lithography tool.

· Development of a 193 nm excimer laser.

· Selection of optical materials for use in and predevelopment of a 193 nm projection system.

· Definition of user requirements for a production exposure tool.

· Resists predevelopment and evaluation.

Participants

GRESSI (F); ASML (NL); Carl Zeiss (D); Exitech (UK); Hereaus (D); IMEC (B); Korth (D); Lambda Physik (D); OCG (CH); RAL (UK).
Contact Point Duration

Jean-Marc Temerson 18 months from 01.02.96

GRESSI

rue des Martyrs 17

F-38054 Grenoble (France)
tel: [phone]

fax: [phone]

E-mail: [e-mail]

EP 20492 SUMMIT

Silicon substrate multi-chip modules for innovative products
Summary

A cost-efficient, commercial manufacturing base is to be established in silicon-based multi-chip modules (MCMs) with active substrates and ball grid array interconnects. The new feature of this technology is the integration of passive and active components in the substrate which would otherwise be connected to an MCM via wirebonding. The first level connection of the standard ICs to the substrate is done using a flip chip interconnect. Development of a commercial source for wafer rerouting to facilitate flip chip interconnects also constitutes a major project goal.

Objectives

· Industrial production procedures for the manufacture of marketable products are to be developed from the basic technology. Special substrates and MCMs will be produced to evaluate the parameters of this technology.

· Cost optimisation of both the MCM architecture and the MCM manufacturing process will be performed throughout.
· Cell libraries for both active and passive components to be used in the design of substrates will be made available.
· Various built in test structures are to be designed and integrated on to silicon substrates. In this way the testability of MCMs can be improved by the use of active substrates.
· A set of analogue and digital simulation cells is to be designed and made available for simulation of the substrate system before production.
· Operative MCMs demonstrating the tools and technologies developed are to be produced. These will undergo a full characterisation to ensure that they comply with the requirements of specific applications in terms of reliability and quality.
Participants

Dicryl SA (E); CNM (E); Dassault Electronique (F); Sibet GmbH (D); NMRC (IRL); ETH Zürich (CH); D+T (E) IN2P3 (F).
Contact Point Duration

Carlos López Requeijo 36 months from 01.12.95

Dicryl SA

Parque Technológico de Boecillo

Boecillo 47151 VALLADOLID (España)
tel: [phone]

fax: [phone]

E-mail: [e-mail]

EP 20797 GOOD-DIE

Get Organised Our Dissemination of Die Information in Europe
Summary

For large scale MCM manufacture with high assembly yields, an infrastructure is required for KGD sourcing as well as a means for the design and simulation of MCMs before committing them to hardware.

This project will create an international electronic database with all the necessary components of bare die. An on-line database will be generated for the location of bare die of all types to carry out the initial selection for components for MCM or hybrid design. A second part of the database will be for design of MCMs or hybrids by downloading electronically the footprints, signal identities, wire bond positions etc. to CAD design workstations for the physical layout of MCMs. Also to be downloaded, if appropriate, will be the device simulation models such as IBIS, VHDL, BHDL, SPICE etc. the database will include all assembly technologies such as wire bond, TAB, flip-chip and chip size package (CSP), if available. Levels of Goodness will be identified from wafer probed to fully burnt-in KGD. (See also EP 20796 GOOD-DIE NETWORK.)
Objectives

· To generate an electronic selection database for the sourcing of KGD.

· To generate an electronic design database for the design of MCMs using KGD by downloading data of die footprints, test data etc. to CAD MCM design and layout workstations. This will include an assessment of the standards and norms regarding KGDs in Europe and the RoW.

· A definition of the requirements of a database for KGD through assessing standards, manufacturer and user requirements for KGD.

· A database for the selection of KGD for MCM design.

· A detailed KGD database for the design, manufacture and test of MCMs.